Method and structure for semiconductor device having gate spacer protection layer
A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.
1. A device comprising:
a first gate stack disposed over a substrate, the first gate stack including a first gate electrode and a first dielectric layer disposed over a first portion of the first gate electrode;
a first contact extending to and interfacing with a second portion of the first gate electrode and the first dielectric layer;
a first gate spacer disposed on a first side of the first gate stack, the first gate spacer interfacing with the first contact;
a second gate spacer disposed on a second side of the first gate stack, the second gate spacer interfacing with the first dielectric layer;
a first etch stop layer disposed directly on a first outer sidewall of the first gate spacer and disposed directly on a second outer sidewall of the second gate spacer; and
a spacer protection layer including a first portion and a second portion, the first portion of the spacer protection layer disposed directly on the first etch stop layer that is disposed directly on the first outer sidewall of the first gate spacer, the first portion of the spacer protection layer extending to the first contact, the second portion of the spacer protection layer disposed directly on the first etch stop layer that is disposed directly on the second outer sidewall of the second gate spacer, the second portion of the spacer protection layer extending to the first dielectric layer; and
a second etch stop layer disposed directly on the first portion of the spacer protection layer, the second portion of the spacer protection layer and the first dielectric layer.
2. The device of claim 1 , further comprising:
a second gate stack disposed over the substrate, the second gate stack including a second gate electrode and a second dielectric layer disposed over a first portion and a third portion of the second gate electrode; and
a second contact extending to and interfacing with a second portion of the second gate electrode and the second dielectric layer, the second portion of the second gate electrode disposed between the first and third portions of the second gate electrode.
3. The device of claim 1 , wherein the first contact extends through and interfaces with the second etch stop layer, and wherein the second contact extends through and interfaces with the second etch stop layer.
4. The device of claim 1 , wherein the spacer protection layer interfaces with the second dielectric layer such that the second dielectric layer prevents the spacer protection layer from interfacing with the second contact.
5. The device of claim 1 , wherein the first portion of the spacer protection layer and the second portion of the spacer protection layer extend to the same height above the substrate.
6. A device comprising:
a first gate stack disposed over a substrate, the first gate stack including a first gate electrode and a first dielectric layer disposed over a first portion of the first gate electrode;
a first contact extending to and interfacing with a second portion of the first gate electrode and the first dielectric layer;
a first gate spacer disposed on the first gate stack;
a second gate spacer disposed on the first gate stack;
a first etch stop layer disposed on a first sidewall of the first gate spacer and a second sidewall of the second gate spacer;
a spacer protection layer including a first portion and a second portion, the first portion of the spacer protection layer disposed directly on the first etch stop layer disposed on the first sidewall of the first gate spacer and extending to the first contact, the second portion of the spacer protection layer disposed directly on the first etch stop layer disposed on the second sidewall of the second gate spacer and extending to the first dielectric layer; and
a second etch stop layer disposed directly on the first and second portions of the spacer protection layer and extending to the first contact.
7. The device of claim 6 , wherein the first gate spacer has an inner sidewall surface facing the first dielectric layer, and wherein the first contact is disposed along and interfacing with the inner sidewall surface of the first gate spacer.
8. The device of claim 6 , wherein the first gate spacer is disposed along a first side of the first gate stack and the second gate spacer is disposed along a second side of the second gate stack that is opposite the first side of the first gate stack, and wherein the first and second gate spacers extend to substantially the same height above the substrate.
9. The device of claim 6 , wherein the second portion of the spacer protection layer is disposed directly on the second gate spacer.
10. The device of claim 6 , wherein a top surface of the first dielectric layer is covered by the second etch stop layer, and wherein the top surface of the first dielectric layer is free of the spacer protection layer.
11. The device of claim 6 , further comprising:
a second gate stack disposed over the substrate, the second gate stack including a second gate electrode and a second dielectric layer disposed entirely over the second gate electrode;
a third gate spacer disposed along a first side of the second gate stack; and
a fourth gate spacer disposed along a second side of the second gate stack, the second side of the second gate stack being opposite the first side, the third gate spacer having an inner sidewall surface facing an inner sidewall surface of the fourth gate spacer, and the second dielectric layer interfacing with the inner sidewall surfaces of the third gate spacer and the fourth gate spacer.
12. The device of claim 11 , further comprising a second contact extending through the second etch stop layer and the second dielectric layer to the second gate electrode.
13. The device of claim 11 , wherein the second dielectric layer extend continuously from the inner sidewall surface of the third gate spacer to the inner sidewall surface of the fourth gate spacer.
14. The device of claim 6 , wherein the first etch stop layer disposed on the sidewall of the first gate spacer has a top surface facing away from the substrate and wherein the first gate spacer has a top surface facing away from the substrate such that the top surfaces of the first gate spacer and the first etch stop layer form a planarized surface.
15. A device comprising:
a first gate stack disposed over a substrate, the first gate stack including a first gate electrode and a first dielectric layer disposed over the first gate electrode;
a first gate spacer disposed along a first side of the first gate stack;
a second gate spacer disposed along a second side of the first gate stack, the second side being opposite the first side;
a first etch stop layer disposed directly on an outer sidewall of the first gate spacer and disposed directly on an outer sidewall of the second gate spacer;
a first contact extending to and interfacing with the first gate spacer and the first etch stop layer disposed directly on the outer sidewall of the first gate spacer;
a spacer protection layer disposed directly on the first etch stop layer that is disposed directly on the second gate spacer, the spacer protection layer extending to the first dielectric layer; and
a second etch stop layer disposed directly on the spacer protection layer and the first dielectric layer, the second etch stop layer further interfacing with the first contact.
16. The device of claim 15 , wherein the first contact interfaces with a first sidewall of the first dielectric layer and the spacer protection layer interfaces with a second sidewall of the first dielectric layer, the second sidewall being opposite the first sidewall of the first dielectric layer.
17. The device of claim 15 , wherein the first gate spacer interfaces with the first sidewall of the first dielectric layer and the second gate spacer interfaces with the second sidewall of the first dielectric layer.
18. The device of claim 15 , further comprising a source/drain feature disposed on the substrate, the first contact being electrically coupled to the source/drain feature.
19. The device of claim 15 , further comprising:
a second gate stack disposed over the substrate, the second gate stack including a second gate electrode and a second dielectric layer disposed over a first portion of the second gate electrode;
a second contact extending to and interfacing with a second portion of the second gate electrode and a first side surface of the second dielectric layer;
a third gate spacer disposed along a first side of the second gate stack;
a fourth gate spacer disposed along a second side of the second gate stack, the second side being opposite the first side;
the first etch stop layer disposed on a sidewall of the third gate spacer; and
the spacer protection layer disposed on the first etch stop layer that is disposed on the sidewall of the third gate spacer and extending to the first side surface of the second dielectric layer, wherein the spacer protection layer further interfaces with a second side surface of the second dielectric layer, the second side surface being opposite the first side surface.
20. The device of claim 19 , further comprising:
a third dielectric layer disposed along and interfacing with the first etch stop layer that is disposed on the sidewall of the third gate spacer; and
a fourth dielectric layer disposed along and interfacing with the spacer protection layer disposed directly on the first etch stop layer that is disposed directly on the second gate spacer, the fourth dielectric layer being formed of a different material than the third dielectric layer.