Structure and method for FinFET device with asymmetric contact

1. A method of forming an integrated circuit structure, the method comprising:

forming a shallow trench isolation (STI) structure in a semiconductor substrate of a first semiconductor material, thereby defining a plurality of fin-type active regions separated from each other by the STI structure;

forming gate stacks on the fin-type active regions;

forming an inter-layer dielectric (ILD) layer filling in gaps between the gate stacks;

patterning the ILD layer to form a trench between adjacent two of the gate stacks;

depositing a first dielectric material layer that is conformal in the trench;

filling the trench with a second dielectric material layer;

patterning the second dielectric material layer to form a contact opening; and

filling a conductive material in the contact opening to form a contact feature.

2. The method of claim 1 , wherein the depositing of the first dielectric material layer includes depositing a high-k dielectric material layer.

3. The method of claim 2 , wherein the depositing of the high-k dielectric material layer includes directly disposing the high-k dielectric material layer on a gate spacer of the gate stacks.

4. The method of claim 1 , wherein the patterning of the second dielectric material layer to form a contact opening includes patterning the second dielectric material layer to form an elongated opening that spans to expose at least two source/drain regions of the fin-type active regions.

5. The method of claim 1 , wherein the forming of the gate stacks includes

forming a dummy gate stack at first ends of the fin-type active regions; and

forming a first gate spacer and a second gate spacer on opposite sidewalls of the dummy gate stack, wherein the first gate spacer lands on the STI structure and the second gate spacer lands on the fin active regions.

6. The method of claim 1 , wherein the filling of the conductive material in the contact opening to form a contact feature includes depositing the conductive material directly on sidewalls of the first and second dielectric material layers.

7. The method of claim 1 , after the patterning of the second dielectric material layer to form a contact opening, further comprising etching back the first dielectric material layer such that the first dielectric material layer on a bottom surface of the contact opening is removed.

8. The method of claim 1 , wherein the forming of the gate stacks on the fin-type active regions includes:

forming dummy gate stacks prior to the forming of the ILD layer;

removing the dummy gate stacks, resulting in gate trenches in the ILD layer; and

filling gate materials in the gate trenches to form the gate stacks, wherein the gate stacks includes a high-k dielectric material on bottom surfaces and sidewalls of the gate trenches, and a metal-containing conductive material on the high-k dielectric material layer.

9. A method of forming an integrated circuit structure, the method comprising:

forming a shallow trench isolation (STI) structure in a semiconductor substrate of a first semiconductor material, thereby defining a plurality of fin-type active regions separated from each other by the STI structure;

forming dummy gate stacks on the fin-type active regions;

forming an inter-layer dielectric (ILD) layer filling in gaps between the dummy gate stacks;

removing the dummy gate stacks, resulting in gate trenches;

forming metal gate stacks in the gate trenches;

patterning the ILD layer to form a trench between adjacent two of the metal gate stacks;

depositing a first dielectric material layer that is conformal in the trench;

filling the trench with a second dielectric material layer;

patterning the second dielectric material layer to form a contact opening; and

filling a conductive material in the contact opening to form a contact feature.

10. The method of claim 9 , wherein the depositing of the first dielectric material layer includes depositing a high-k dielectric layer of a first high-k dielectric material.

11. The method of claim 10 , wherein the forming of the metal gate stacks includes depositing a gate dielectric layer and depositing a conductive material layer on the gate dielectric layer, wherein the gate dielectric layer includes a second high-k dielectric material different from the first high-k dielectric material in composition.

12. The method of claim 10 , further comprising forming gate spacers on sidewalls of the dummy gate stacks, wherein the depositing of the high-k dielectric layer includes directly disposing the high-k dielectric layer on the gate spacers.

13. The method of claim 10 , wherein the filling of the conductive material in the contact opening to form the contact feature includes depositing the conductive material directly on sidewalls of the high-k dielectric layer and sidewalls of the second dielectric material layer.

14. The method of claim 9 , further comprising forming two epitaxially grown source/drain features on the fin-type active regions after the patterning of the ILD layer to form the trench between adjacent two of the metal gate stacks, wherein the patterning of the second dielectric material layer to form the contact opening includes patterning the second dielectric material layer to form an elongated opening that spans to expose the two epitaxially grown source/drain features.

15. A method, comprising:

forming a fin-type active region extruded from a semiconductor substrate;

forming a gate stack on the fin-type active region;

forming a source/drain feature in the fin-type active region, wherein the source/drain feature is disposed on a side of the gate stack;

forming an elongated contact feature landing on the source/drain feature; and

forming a dielectric material layer disposed on sidewalls of the elongated contact feature, wherein the a dielectric material layer is free from ends of the elongated contact feature, and wherein the sidewalls of the elongated contact feature are parallel with the gate stack.

16. The method of claim 15 , wherein

the forming of the gate stack includes forming a gate dielectric feature, forming a gate electrode on the gate dielectric feature, and forming a spacer on sidewalls of the gate electrode; and

the forming of the dielectric material layer includes forming the dielectric material layer interposed between the gate stack and the elongated contact feature, and directly contacting the spacer and the elongated contact feature.

17. The method of claim 16 , wherein the forming of the gate dielectric feature includes a first high k dielectric material and the forming of the dielectric material layer includes forming a second high k dielectric material different from the first high k dielectric material in composition.

18. The method of claim 17 , wherein the forming of the dielectric material layer includes forming the dielectric material layer recessed from the elongated contact feature such that a top surface of the dielectric material layer is below a top surface of the elongated contact feature.

19. The method of claim 15 , further comprising forming a shallow trench isolation (STI) feature on the semiconductor substrate and surrounding the fin-type active region.

20. The method of claim 19 , further comprising forming a second gate stack partially landing on an end of the fin-type active region and partially landing on the STI feature.