Interconnect structure and method for forming the same
Embodiments of an interconnect structure and methods for forming an interconnect structure are provided. The method includes forming a low-k dielectric layer over a substrate, forming an opening in the low-k dielectric layer, forming a conductor in the opening, forming a capping layer over the conductor, and forming an etch stop layer over the capping layer and the low-k dielectric layer. The etch stop layer includes an N element with a content ratio not less than about 25 at %.
1. A method, comprising:
forming a low-k dielectric layer over a substrate;
forming an opening in the low-k dielectric layer;
forming a conductor in the opening;
forming a capping layer over the conductor; and
forming an etch stop layer over the capping layer and the low-k dielectric layer, wherein the etch stop layer includes an N element with a content ratio ranging from about 25 at % to about 40 at %, and wherein the etch stop layer has a dielectric constant ranging from about 5.7 to about 6.8.
2. The method of claim 1 , wherein the capping layer includes Co, CoWP, AlN, or combinations thereof.
3. The method of claim 1 , wherein the capping layer is Co layer formed using CPCo(CO) 2 and NH 3 .
4. The method of claim 1 , wherein the etch stop layer is SiCN.
5. The method of claim 4 , wherein the SiCN includes a C element with a content ratio ranging from about 5 at % to about 25 at %.
6. The method of claim 1 , wherein the etch stop layer includes a Si element with a content ratio less than about 50 at %.
7. The method of claim 1 , wherein the etch stop layer includes a C element with a content ratio ranging from about 5 at % to about 25 at %.
8. The method of claim 1 , wherein the etch stop layer has a thickness ranging about 10 angstroms to about 300 angstroms.
9. The method of claim 1 , wherein the low-k dielectric layer has a dielectric constant ranging from about 2.3 to about 2.6.
10. The method of claim 1 , further comprising forming an adhesion layer under the low-k dielectric layer.
11. A method, comprising:
forming a first etch stop layer over a substrate;
forming an adhesion layer over the first etch stop layer;
forming a low-k dielectric layer over the adhesion layer;
forming an opening in the low-k dielectric layer, the adhesion layer, and the first etch stop layer;
forming a metal line in the opening, wherein a surface of the metal line facing away from the substrate and a surface of the low-k dielectric layer facing away from the substrate are substantially co-planar;
selectively forming a capping layer over the metal line; and
forming a second etch stop layer over the capping layer and the low-k dielectric layer, wherein the etch stop layer includes an N element with a content ratio ranging from about 25 at % to about 40 at %.
12. The method of claim 11 , wherein the adhesion layer comprises a second adhesion layer over a first adhesion layer.
13. The method of claim 11 , wherein the capping layer includes Co, CoWP, AlN, or combinations thereof.
14. The method of claim 11 , wherein a Co element in the capping layer forms a bond with the N element in the etch stop layer.
15. The method of claim 11 , wherein a Co element in the capping layer forms a bond with a Cu element in the metal line.
16. The method of claim 11 , wherein the capping layer is formed by introducing gases of CPCo(CO) 2 and NH 3 over the substrate.
17. A semiconductor device, comprising:
a low-k dielectric layer over a substrate;
a conductor in the low-k dielectric layer;
a capping layer over the conductor; and
an etch stop layer over the capping layer and the low-k dielectric layer, wherein the etch stop layer includes an N element with a content ratio ranging from about 25 at % to about 40 at %, and wherein the etch stop layer has a dielectric constant ranging from about 5.7 to about 6.8.
18. The semiconductor device of claim 17 , wherein the capping layer includes Co, CoWP, AlN, or combinations thereof.
19. The semiconductor device of claim 17 , wherein the low-k dielectric layer has a dielectric constant ranging from about 2.3 to about 2.6.
20. The semiconductor device of claim 17 , wherein the etch stop layer includes a C element with a content ratio ranging from about 5 at % to about 25 at %.