Bump structural designs to minimize package defects

1. A method of forming a chip package, comprising:

providing a chip with a plurality of first copper post bumps, wherein the plurality of first copper post bumps have a first height of copper post;

providing a substrate with a plurality of second copper post bumps, wherein the plurality of second copper post bumps have a second height of copper post;

bonding the plurality of first copper post bumps to the plurality of second copper post bumps by reflowing solder layers on the plurality of first copper post bumps and the plurality of second copper post bumps together to form a first copper post bump structure of the chip package, wherein the first copper post bump structure has a standoff, wherein a ratio of a sum of the first height of copper post and the second height of copper post to the standoff is equal to or greater than about 0.6 and less than 1.

2. The method of claim 1 , further comprising:

applying flux on the plurality of first copper post bumps and the plurality of second copper post bumps prior to the bonding; and

removing the flux from between the chip and the substrate after the bonding, wherein substantially no residue remains on the chip package after the removing flux.

3. The method of claim 1 , further comprising:

forming an underfill between the chip and the substrate after the bonding, wherein the underfill contains substantially no voids.

4. The method of claim 1 , wherein the widths of the first plurality of copper post bumps and the second plurality of copper post bumps are equal to or less than about 30 microns (μm).

5. The method of claim 1 , wherein the pitches of the plurality of first copper post bumps and the plurality of second copper post bumps are equal to or less than about 60 μm.

6. The method of claim 1 , wherein the aspect ratios of the plurality of first copper post bumps and the plurality of second copper post bumps are equal to or greater than about 0.45.

7. The method of claim 1 , wherein the standoff is equal to or greater than about 30 μm.

8. A method of forming a chip package, comprising:

forming a plurality of first copper posts on a chip, wherein at least one first copper post of the plurality of first copper posts has a first height;

forming a plurality of second copper posts on a substrate, wherein at least one second copper post of the plurality of second copper posts has a second height;

bonding each first copper post of the plurality of first copper posts to a corresponding second copper post of the plurality of second copper posts to form a bonded post structure, wherein the bonded post structure has a standoff equal to or greater than 30 microns (μm), and bonding each first copper post of the plurality of first copper posts to a corresponding second copper post of the plurality of second copper posts comprises applying flux to at least one of the plurality of first copper posts or the plurality of second copper posts; and

forming an underfill between the chip and the substrate, wherein the underfill is free of voids.

9. The method of claim 8 , wherein forming the plurality of first copper posts comprises:

plating a copper layer on the chip;

forming a metal layer on the copper layer; and

forming a solder layer on the metal layer.

10. The method of claim 9 , wherein forming the metal layer comprises plating a nickel-containing layer.

11. The method of claim 9 , wherein forming the metal layer comprises forming a layer comprising at least one of cobalt or tungsten.

12. The method of claim 8 , further comprising removing the applied flux following the bonding process, wherein removing the applied flux comprises at least one of applying a solvent, applying de-ionized water, or heating the bonded post structure.

13. The method of claim 8 , wherein forming the underfill comprises injecting the underfill in a space between the chip and the substrate.

14. The method of claim 8 , further comprising curing the underfill.

15. A method of forming a chip package, the method comprising:

forming a first copper post on a chip, the first copper post having a first height, wherein a first width of the first copper post is equal to or less than about 30 microns (μm);

forming a second copper post on a substrate, the second copper post having a second height; and

bonding the second copper post to the first copper post using a solder layer to form a first copper post bump structure of the chip package with a standoff, wherein a ratio of a sum of the first height and the second height to the standoff is equal to or greater than about 0.6 and less than 1, and sidewall surfaces of the first copper post and sidewall surfaces of the second copper post are free of the solder layer.

16. The method of claim 15 , further comprising forming an underfill between the chip and the substrate, wherein the underfill contains substantially no voids.

17. The method of claim 15 , further comprising forming a second copper post bump structure next to the first copper post bump structure, wherein a pitch between the first copper post bump structure and the second copper post bump structure is equal to or less than about 60 μm.

18. The method of claim 15 , wherein forming the first copper post comprises forming the first copper post with an aspect ratio equal to or greater than about 0.45.

19. The method of claim 15 , wherein bonding the second copper post to the first copper post using a solder layer comprises forming the standoff equal to or greater than about 30 microns μm.

20. The method of claim 15 , further comprising applying flux to at least one of the plurality of first copper posts or the plurality of second copper posts.