Source/drain regions for fin field effect transistors and methods of forming same

1. A semiconductor device comprising:

a fin extending upwards from a semiconductor substrate;

a gate stack disposed over a top surface and sidewalls of the fin;

a first source/drain region over the semiconductor substrate and adjacent the gate stack;

a shallow trench isolation (STI) region below the gate stack and adjacent the fin; and

a first source/drain spacer on a sidewall of the first source/drain region, wherein a portion of the first source/drain region extends under a bottom surface of the first source/drain spacer, wherein the first source/drain spacer is spaced apart from the STI region, and wherein at least a portion of the first source/drain region is disposed between the STI region and the first source/drain spacer in a direction normal to a bottom surface of the semiconductor substrate.

2. The semiconductor device of claim 1 further comprising:

a second source/drain region over the semiconductor substrate and adjacent the gate stack, wherein the first and second source/drain regions are disposed on a same side of the gate stack; and

a second source/drain spacer on a sidewall of the second source/drain region, wherein a portion of the second source/drain region extends under a bottom surface of the second source/drain spacer.

3. The semiconductor device of claim 2 further comprising an epitaxy region connecting the first source/drain region to the second source/drain region.

4. The semiconductor device of claim 3 , wherein the epitaxy region is disposed over and contacts a top surface of the STI region, wherein the STI region is disposed between the first and second source/drain regions.

5. The semiconductor device of claim 3 , wherein the epitaxy region extends upwards between sidewalls of the first source/drain spacer and the second source/drain spacer.

6. The semiconductor device of claim 1 , further comprising a gate spacer on a sidewall of the gate stack, wherein the first source/drain spacer is connected to the gate spacer, and wherein no interface is formed between the first source/drain spacer and the gate spacer.

7. The semiconductor device of claim 6 , wherein the gate stack comprises:

a gate dielectric, wherein a portion of the gate dielectric is disposed under a bottom surface of the gate spacer; and

a gate electrode over the gate dielectric.

8. A semiconductor device comprising:

a fin extending upwards from a semiconductor substrate;

a gate stack over and extending along sidewalls of the fin;

a first shallow trench isolation (STI) region below the gate stack and adjacent the fin;

a sidewall spacer over the first STI region and extending along a sidewall of the gate stack, wherein the sidewall spacer is separated from the first STI region;

a source/drain region adjacent the fin, wherein the source/drain region extends between the first STI region and the sidewall spacer along a line perpendicular to a major surface of the semiconductor substrate.

9. The semiconductor device of claim 8 , wherein an epitaxy material of the source/drain region extends continuously between opposing sidewalls of the first STI region in a cross sectional view.

10. The semiconductor device of claim 8 , wherein an epitaxy material of the source/drain region contacts opposing sidewalls of the sidewall spacer in a cross sectional view.

11. The semiconductor device of claim 8 further comprising a second STI region on an opposing side of the source/drain region as the first STI region, wherein the source/drain region extends below a top surface of the second STI region.

12. The semiconductor device of claim 11 , wherein the sidewall spacer is disposed over the second STI region, and wherein the source/drain region extends between the second STI region and the sidewall spacer along a line perpendicular to the major surface of the semiconductor substrate.

13. The semiconductor device of claim 8 , wherein the gate stack comprises a gate dielectric and a gate electrode over the gate dielectric, wherein the gate dielectric is disposed between the gate electrode and the sidewall spacer along a line parallel to the major surface of the semiconductor substrate.

14. The semiconductor device of claim 13 , wherein the gate dielectric extends under a bottom surface of the sidewall spacer.

15. The semiconductor device of claim 8 further comprising an additional source/drain region adjacent the fin, and wherein the source/drain region and the additional source/drain region are physically separated.

16. A device comprising:

a semiconductor fin protruding from a major surface of a substrate;

a first shallow trench isolation (STI) region and a second STI region disposed on opposing sides of the semiconductor fin, wherein a surface of the semiconductor fin is lower than top surfaces of the first STI region and the second STI region;

a first source/drain region on the surface of the semiconductor fin between the first STI region and the second STI region;

a sidewall spacer extending along sidewalls of the first source/drain region, wherein the sidewall spacer is spaced apart from the first STI region, and wherein a semiconductor material is disposed between the sidewall spacer and the first STI region along a line perpendicular to a major surface of the substrate.

17. The device of claim 16 , wherein the semiconductor material connects the first source/drain region to a second source/drain region, wherein the first source/drain region and the second source/drain region are disposed on opposing sides of the first STI region.

18. The device of claim 16 , wherein the semiconductor material forms an interface with a sidewall of the sidewall spacer opposite the first source/drain region.

19. The device of claim 16 further comprising a gate stack over and extending along sidewalls of the semiconductor fin, wherein the sidewall spacer further extends along sidewalls of the gate stack.

20. The device of claim 19 , wherein the gate stack comprises a gate dielectric disposed between the sidewall spacer and the substrate along a line perpendicular to the major surface of the substrate.