Multi-gate device structure including a fin-embedded isolation region and methods thereof
A structure and method for implementation of high voltage devices within multi-gate device structures includes a substrate having a fin extending therefrom and a fin-embedded isolation region. In some examples, the fin-embedded isolation region includes an STI region. In some embodiments, the fin-embedded isolation separates a first portion of the fin from a second portion of the fin. Also, in some examples, the first portion of the fin includes a channel region. In various embodiments, a source region is formed in the first portion of the fin, a drain region is formed in the second portion of the fin, and an active gate is formed over the channel region. In some examples, the active gate is disposed adjacent to the source region. In addition, a plurality of dummy gates may be formed over the fin, to provide a uniform growth environment and growth profile for source and drain region formation.
1. A device, comprising:
a substrate including at least one fin extending therefrom;
a fin-embedded isolation region that extends into the substrate and separates a first portion of the at least one fin from a second portion of the at least one fin, wherein the first portion of the at least one fin includes a channel region; and
a source region formed in the first portion of the at least one fin and a drain region formed in the second portion of the at least one fin.
2. The device of claim 1 , further comprising:
an active gate formed over the channel region, wherein the active gate is disposed adjacent to a first side of the source region.
3. The device of claim 1 , wherein the device includes a high voltage semiconductor device.
4. The device of claim 1 , further comprising:
the substrate including a plurality of fins extending therefrom, wherein the plurality of fins includes the at least one fin; and
wherein the fin-embedded isolation region spans the plurality of fins and separates a first portion of each fin of the plurality of fins from a second portion of each fin of the plurality of fins.
5. The device of claim 1 , wherein the fin-embedded isolation region includes a shallow trench isolation (STI) region.
6. The device of claim 1 , further comprising a first extension region adjacent to and between the channel region and the fin-embedded isolation region, and a second extension region adjacent to and between the fin-embedded isolation region and the drain region.
7. The device of claim 1 , further comprising a plurality of dummy gates disposed over the fin.
8. A method, comprising:
providing a substrate including a plurality of fins extending therefrom;
forming a fin-embedded isolation region that spans the plurality of fins and separates a first portion of each fin of the plurality of fins from a second portion of each fin of the plurality of fins, wherein a first portion of at least one fin of the plurality of fins includes a channel region;
forming a source region in the first portion of the at least one fin; and
forming a drain region, at a selected distance from the fin-embedded isolation region, in the second portion of the at least one fin, wherein the selected distance is chosen to provide a selected fin resistance.
9. The method of claim 8 , further comprising:
forming an active gate over the channel region of the at least one fin, wherein the active gate is disposed adjacent to the source region.
10. The method of claim 8 , wherein the forming the fin-embedded isolation region includes forming a shallow trench isolation (STI) region that extends into the substrate.
11. The method of claim 10 , wherein responsive to forming the STI region that extends into the substrate, forming a conductive path between the source region and the drain region that traverses at least a portion of the substrate under the STI region.
12. The method of claim 8 , further comprising:
forming a first extension region within the at least one fin, wherein the first fin extension region is adjacent to and between the channel region and the fin-embedded isolation region.
13. The method of claim 12 , further comprising:
forming a second extension region within the at least one fin, wherein the second fin extension region is adjacent to and between the fin-embedded isolation region and the drain region.
14. The method of claim 8 , further comprising:
forming a plurality of dummy gates disposed over the at least one fin.
15. A method of semiconductor device fabrication, comprising:
providing a substrate including a fin extending therefrom;
forming a fin-embedded isolation region that separates a first portion of the fin from a second portion of the fin, wherein the first portion of the fin includes a channel region;
providing, by a plurality of dummy gates formed over the fin, a uniform growth environment for subsequent formation of a source region and a drain region; and
forming the source region in the first portion of the fin and the drain region in the second portion of the fin.
16. The method of claim 15 , further comprising:
forming an active gate over the channel region, wherein the active gate is disposed adjacent to a first side of the source region.
17. The method of claim 15 , wherein the forming the fin-embedded isolation region includes forming a shallow trench isolation (STI) region that extends into the substrate.
18. The method of claim 15 , wherein the uniform growth environment provides a uniform epitaxial growth profile for both of the source region and the drain region.
19. The method of claim 15 , wherein a pair of dummy gates of the plurality of dummy gates are disposed adjacent to and on either side of the drain region.
20. The method of claim 19 , wherein a dummy gate of the plurality of dummy gates is disposed adjacent to a second side of the source region.