Integrated circuits and methods of forming integrated circuits
An integrated circuit includes a gate electrode and spacers along sidewalls of the gate electrode. The integrated circuit further includes a source/drain (S/D) region adjacent to the gate electrode. The S/D region includes a diffusion barrier structure at least partially in a recess of the substrate. The diffusion barrier structure includes an epitaxial layer having a first region and a second region. The first region is thinner than the second region, and the first region is misaligned with respect to the sidewalls of the gate electrode. The S/D region includes a doped silicon-containing structure over the diffusion barrier structure. The first region of the diffusion barrier structure is configured to partially prevent dopants of the doped silicon-containing structure from diffusing into the substrate. The second region of the diffusion barrier structure is configured to substantially completely prevent the dopants of the doped silicon-containing structure from diffusing into the substrate.
1. An integrated circuit comprising:
a gate electrode over a substrate;
spacers along sidewalls of the gate electrode; and
a source/drain (S/D) region adjacent to the gate electrode, the S/D region comprising:
a diffusion barrier structure at least partially in a recess of the substrate, wherein the diffusion barrier structure comprises an epitaxial layer extending underneath at least a portion of the spacers, the epitaxial layer comprises a first region and a second region, wherein the first region is thinner than the second region, and the first region is misaligned with respect to the sidewalls of the gate electrode; and
a doped silicon-containing structure over the diffusion barrier structure, wherein the first region of the diffusion barrier structure is configured to partially prevent dopants of the doped silicon-containing structure from diffusing into the substrate and the second region of the diffusion barrier structure is configured to substantially completely prevent the dopants of the doped silicon-containing structure from diffusing into the substrate.
2. The integrated circuit of claim 1 , wherein an inner sidewall of the first region is displaced from a plane along the sidewall of the gate electrode, and a displacement is in a direction parallel to a top surface of the substrate.
3. The integrated circuit of claim 2 , wherein the inner sidewall of the first region is located closer to a center of the gate electrode than the plane along the sidewall of the gate electrode.
4. The integrated circuit of claim 2 , wherein the inner sidewall of the first region is located farther from a center of the gate electrode than the plane along the sidewall of the gate electrode.
5. The integrated circuit of claim 2 , wherein the inner sidewall is displaced from the plane along the sidewall of the gate electrode by a distance of 10 nanometers (nm) or less.
6. The integrated circuit of claim 2 , wherein an outer sidewall of the first region is on an opposite side of the plane along the sidewall of the gate electrode than the inner sidewall.
7. The integrated circuit of claim 1 , wherein a thickness of the first region is variable along a length of the first region.
8. The integrated circuit of claim 1 , wherein a depth of the first region from a top surface of the substrate is 7 nm or less.
9. The integrated circuit of claim 1 , wherein a thickness of the first region is constant along a length of the first region.
10. An integrated circuit comprising:
a gate electrode over a substrate; and
a source/drain (S/D) region adjacent to the gate electrode, the S/D region comprising:
a diffusion barrier structure at least partially in a recess of the substrate, wherein the diffusion barrier structure comprises an epitaxial layer, wherein the epitaxial layer comprises a first region and a second region, wherein the first region is thinner than the second region, and a first portion of the first region extends underneath the gate electrode; and
a doped silicon-containing structure over the diffusion barrier structure, wherein the first region of the diffusion barrier structure is configured to partially prevent dopants of the doped silicon-containing structure from diffusing into the substrate and the second region of the diffusion barrier structure is configured to substantially completely prevent the dopants of the doped silicon-containing structure from diffusing into the substrate.
11. The integrated circuit of claim 10 , wherein a second portion of the first region extends beyond the gate electrode.
12. The integrated circuit of claim 11 , wherein the epitaxial layer comprises carbon.
13. The integrated circuit of claim 11 , wherein an area of a top surface of the substrate contacting the first region is entirely under the gate electrode.
14. The integrated circuit of claim 11 , wherein the first region has a variable thickness.
15. The integrated circuit of claim 11 , wherein the doped-silicon containing structure contacts the first region.
16. An integrated circuit comprising:
a gate electrode over a substrate;
spacers along sidewalls of the gate electrode; and
a source/drain (S/D) region adjacent to the gate electrode, the S/D region comprising:
a diffusion barrier structure at least partially in a recess of the substrate, wherein the diffusion barrier structure comprises an epitaxial layer, wherein the epitaxial layer comprises a first region and a second region, wherein the first region is thinner than the second region, and a first portion of the first region under the spacers; and
a doped silicon-containing structure over the diffusion barrier structure, wherein the doped silicon-containing structure extends underneath at least a portion of the spacers, the first region of the diffusion barrier structure is configured to partially prevent dopants of the doped silicon-containing structure from diffusing into the substrate and the second region of the diffusion barrier structure is configured to substantially completely prevent the dopants of the doped silicon-containing structure from diffusing into the substrate.
17. The integrated circuit of claim 16 , wherein a second portion of the first region is under the gate electrode.
18. The integrated circuit of claim 16 , wherein an entirety of the first region is under the spacers.
19. The integrated circuit of claim 16 , wherein the first region has a variable thickness.