Fin-like field effect transistor (FinFET) device and method of manufacturing same
View Patent ↗A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary device includes a fin structure formed over a semiconductor substrate. The fin structure includes a source region and a drain region that include a first material layer disposed over the semiconductor substrate, a second material layer disposed over the first material layer, and a third material layer disposed over the second material layer. The first, second, and third material layers are different from each other. The fin structure also has a channel defined between the source and drain regions. The channel includes the first material layer disposed over the semiconductor substrate and the second semiconductor material layer disposed over the first material layer.
1. A device comprising:
a fin structure disposed over a semiconductor substrate, the fin structure including:
a source region and a drain region that include a first semiconductor material layer disposed over the semiconductor substrate, a second semiconductor material layer disposed over the first semiconductor material layer, and a third semiconductor material layer disposed over the second semiconductor material layer, wherein the first, second, and third semiconductor material layers are different in composition from each other;
a channel defined between the source and drain regions, the channel including the first semiconductor material layer disposed over the semiconductor substrate and the second semiconductor material layer disposed over the first semiconductor material layer; and
a gate structure in direct contact with a top surface of the second semiconductor material layer of the channel.
2. The device of claim 1 ,
wherein the first semiconductor material layer comprises Si,
wherein the second semiconductor material layer comprises Si 1-x Ge x ,
wherein the third material layer includes a third semiconductor material layer comprises Si 1-z Ge z , and
wherein z is smaller than x.
3. The device of claim 1 , further comprising a fourth semiconductor material layer disposed between the second semiconductor material layer and the third semiconductor material layer in the source and drain regions, wherein the second, third, and fourth semiconductor material layers include different materials from each other.
4. The device of claim 3 , wherein the first semiconductor material layer and the fourth semiconductor material layer are formed of similar materials.
5. The device of claim 1 , further comprising another fin structure formed over the semiconductor substrate, the another fin structure including:
another source region and another drain region that include the first semiconductor material layer disposed over the semiconductor substrate and a fourth semiconductor material layer disposed over the first semiconductor material layer, wherein the first, second, third, and fourth semiconductor material layers are different from each other;
another channel defined between the another source and drain regions, the another channel including the first semiconductor material layer disposed over the semiconductor substrate and the second semiconductor material layer disposed over the first semiconductor material layer; and
another gate in direct contact with the second semiconductor material layer of the another channel.
6. The device of claim 5 , wherein the third semiconductor material layer includes germanium at a first concentration and the fourth semiconductor material layer includes germanium at a second concentration that is different from the first concentration.
7. The device of claim 5 , wherein an upper surface of the fourth semiconductor material layer in the another source region and another drain region of the another fin structure is lower than an upper surface of an isolation feature disposed between the fin structure and the another fin structure relative to an upper surface of the semiconductor substrate.
8. The device of claim 1 , wherein the second semiconductor material layer includes germanium at a first concentration and the third semiconductor material layer includes germanium at a second concentration that is smaller than the first concentration.
9. The device of claim 5 , wherein the second semiconductor material layer includes germanium at a first concentration and the third semiconductor material layer includes germanium at a second concentration that is smaller than the first concentration.
10. The device of claim 1 , further comprising another fin structure formed over the semiconductor substrate, the other fin structure including:
another source region and another drain region that include the first semiconductor material layer disposed over the semiconductor substrate and a fourth semiconductor material layer disposed over the first semiconductor material layer, wherein the third and the fourth semiconductor material layers contain germanium at the same concentration; and
a channel defined between the source and drain regions, the channel including the first semiconductor material layer disposed over the semiconductor substrate and the second semiconductor material layer disposed over the first semiconductor material layer.
11. An integrated circuit device comprising:
a semiconductor substrate; and
an N-type metal oxide semiconductor (NMOS) fin structure disposed over a semiconductor substrate, the NMOS fin structure including:
a source region and a drain region that include a first semiconductor material layer disposed over the semiconductor substrate, a second semiconductor material layer disposed over the first semiconductor material layer, and a third semiconductor material layer disposed over the second semiconductor material layer, wherein the first, second, and third semiconductor material layers are different from each other,
a first channel defined between the source and regions, the first channel including the first semiconductor material layer disposed over the semiconductor substrate and the second semiconductor material layer disposed over the first semiconductor material layer, and
a gate structure in direct contact with the second semiconductor material layer of the first channel from above the second semiconductor material layer.
12. The integrated circuit device of claim 11 , further comprising:
a P-type metal oxide semiconductor (PMOS) fin structure disposed over a semiconductor substrate, the PMOS fin structure including:
another source region and another drain region that include the first semiconductor material layer disposed over the semiconductor substrate and a fourth semiconductor material layer disposed over the first semiconductor material layer,
a second channel defined between the another source and drain regions, the channel including the first semiconductor material layer disposed over the semiconductor substrate and the second semiconductor material layer disposed over the first semiconductor material layer, and,
another gate structure in contact with the second semiconductor layer of the second channel.
13. The integrated circuit device of claim 12 , wherein:
the first semiconductor material layer comprises Si;
the second semiconductor material layer comprises Si 1-x Ge x ;
the third semiconductor material layer comprises Si 1-z Ge z ; and
the fourth semiconductor material layer comprises Si 1-y Ge y .
14. The integrated circuit device of claim 13 , wherein y is independent of x.
15. The integrated circuit device of claim 13 , wherein z is smaller than x.
16. The integrated circuit device of claim 13 , wherein z is the same as y.
17. The integrated circuit device of claim 11 , wherein both the third and fourth semiconductor material layers are epitaxially deposited layers.