Absorption enhancement structure for image sensor
The present disclosure relates to an integrated chip. The integrated chip includes an image sensing element disposed within a substrate. The substrate has a plurality of protrusions disposed along a first side of the substrate over the image sensing element and a ridge disposed along the first side of the substrate. The ridge continuously extends around the plurality of protrusions.
1. An integrated chip, comprising:
an image sensing element disposed within a substrate, wherein the substrate comprises a plurality of protrusions disposed along a first side of the substrate over the image sensing element and a ridge disposed along the first side of the substrate; and
wherein the ridge continuously extends around the plurality of protrusions.
2. The integrated chip of claim 1 , wherein the ridge has a substantially flat upper surface that extends around the plurality of protrusions along a closed loop.
3. The integrated chip of claim 1 , wherein the plurality of protrusions are defined by sidewalls having a cross-sectional profile with a first slope at a first point that is a first distance over the image sensing element and a second slope at a second point that is a second distance over the image sensing element, the second distance larger than the first distance.
4. The integrated chip of claim 1 , further comprising:
a second image sensing element disposed within the substrate, wherein the substrate comprises a second plurality of protrusions disposed along the first side of the substrate over the second image sensing element; and
wherein the ridge continuously extends around the plurality of protrusions along a first closed loop and the ridge continuously extends around the second plurality of protrusions along a second closed loop that shares a side with the first closed loop.
5. The integrated chip of claim 1 , wherein the plurality of protrusions comprise a first protrusion that is defined by a flat surface, and wherein the flat surface is separated from a top of the first protrusion by a non-zero distance.
6. The integrated chip of claim 1 , wherein the plurality of protrusions comprise a first protrusion having a first height, and wherein the first protrusion is defined by a flat surface having a second height that is less than the first height.
7. The integrated chip of claim 1 , wherein the plurality of protrusions comprise a first protrusion having a height and a width measured along largest dimensions of the first protrusion, wherein a ratio between the height and the width is in a range of between approximately 1 and approximately 1.25.
8. The integrated chip of claim 1 , wherein the plurality of protrusions comprise a first protrusion having a height in a range of between approximately 400 nm and approximately 600 nm and having a width in a range of between approximately 400 nm and approximately 500 nm.
9. The integrated chip of claim 1 , wherein the ridge extends in a closed loop that surrounds not more than 16 protrusions and not less than 16 protrusions.
10. An integrated chip, comprising:
a substrate;
an image sensing element disposed within the substrate; and
wherein the substrate has one or more surfaces extending between a bottom and a top of a protrusion over the image sensing element, wherein a slope of the one or more surfaces increases from a first point a first distance over image sensing element to a second point a second distance over the image sensing element, the second distance greater than the first distance.
11. The integrated chip of claim 10 ,
wherein the one or more surfaces of the substrate comprise a first sidewall having a first segment as viewed in a cross-sectional view; and
wherein an imaginary line extending along the first segment intersects a second sidewall of the protrusion opposing the first sidewall.
12. The integrated chip of claim 10 , wherein the one or more surfaces comprise a curved surface.
13. The integrated chip of claim 12 , wherein the one or more surfaces further comprise a flat surface.
14. The integrated chip of claim 13 , wherein the flat surface is vertically between the curved surface and the image sensing element.
15. The integrated chip of claim 13 , wherein the protrusion comprises a height and a width measured along largest dimensions of the protrusion, wherein a ratio between the height and the width is in a range of between approximately 1 and approximately 1.2.
16. An integrated chip, comprising:
an image sensing element disposed within a substrate;
wherein the substrate comprises a plurality of protrusions along a first side of the substrate and a ridge along the first side of the substrate, the ridge surrounding the plurality of protrusions; and
wherein the ridge has a greater width than respective ones of the plurality of protrusions.
17. The integrated chip of claim 16 , wherein the ridge has a different cross-sectional profile than the respective ones of the plurality of protrusions.
18. The integrated chip of claim 16 , wherein the plurality of protrusions comprise a first protrusion having sidewalls that meet at a top of the first protrusion.
19. The integrated chip of claim 16 , wherein the plurality of protrusions comprise a first protrusion separated from a second protrusion by a surface of the substrate having a width of between approximately 0 nm and approximately 15 nm.
20. The integrated chip of claim 16 ,
wherein the plurality of protrusions comprise a first protrusion and a second protrusion; and
wherein a sidewall of the first protrusion intersects a sidewall of the second protrusion.