IP Library Granted Patent US 10,804,315
Granted Patent B2
US 10,804,315 · App. 16/693,627 · Granted Oct 13, 2020

Absorption enhancement structure for image sensor

Inventors: Ching-Chung Su (Tainan, TW); Hung-Wen Hsu (Tainan, TW); Jiech-Fun Lu (Madou Township, TW); Shih-Pei Chou (Tainan, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L27/14685H01L27/1462H01L27/1463H01L27/1464H01L27/14621H01L27/14627H01L27/14643H01L27/14689
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Quick Facts
Patent No.
US 10,804,315
App. No.
16/693,627
Granted
Oct 13, 2020
Kind
B2
Abstract

The present disclosure, in some embodiments, relates to method of forming an integrated chip. The method may be performed by forming an image sensing element within a substrate. A dry etching process is performed on the substrate to form a plurality of intermediate protrusions defined by the substrate. A wet etching process is performed on the plurality of intermediate protrusions to form a plurality of protrusions from the plurality of intermediate protrusions.

Claims (45)

1. A method of forming an integrated chip, comprising:

forming an image sensing element within a substrate;

performing a dry etching process on the substrate to form a plurality of intermediate protrusions defined by the substrate; and

performing a wet etching process on the plurality of intermediate protrusions to form a plurality of protrusions from the plurality of intermediate protrusions.

2. The method of claim 1 , further comprising:

forming a masking layer over the substrate; and

performing the dry etching process on the substrate according to the masking layer to define the plurality of intermediate protrusions.

3. The method of claim 1 , wherein the image sensing element is formed within the substrate prior to performing the dry etching process.

4. The method of claim 1 , wherein the image sensing element is formed within the substrate after performing the dry etching process.

5. The method of claim 1 ,

wherein a first one of the plurality of protrusions has a flat segment as viewed in a cross-sectional view of the plurality of protrusions; and

wherein a line that extends along the flat segment intersects an opposing sidewall of the first one of the plurality of protrusions.

6. The method of claim 1 ,

wherein a horizontally extending surface having a first width extends between adjacent ones of the plurality of intermediate protrusions; and

wherein the wet etching process reduces a width of the horizontally extending surface from the first width to a second width smaller than the first width.

7. The method of claim 1 ,

wherein the substrate has one or more surfaces extending between a bottom and a top of a first one of the plurality of protrusions; and

wherein a slope of the one or more surfaces increases from a first point a first distance over the image sensing element to a second point a second distance over the image sensing element, the second distance greater than the first distance.

8. A method of forming an integrated chip, comprising:

performing a dry etch on a first side of a substrate to define a plurality of intermediate protrusions having sidewalls oriented at a first angle with respect to a horizontal plane that is parallel to a second side of the substrate opposing the first side; and

performing a second etch on the plurality of intermediate protrusions to reduce an angle of the sidewalls and define a plurality of protrusions.

9. The method of claim 8 , further comprising:

forming a ridge along the first side of the substrate, wherein the ridge has an uppermost surface that is configured to continuously extend in a closed path around the plurality of protrusions.

10. The method of claim 9 , wherein a second horizontal plane extends along the uppermost surface of the ridge and is separated from the plurality of protrusions by one or more non-zero distances.

11. The method of claim 9 , wherein the ridge has a greater width than a respective one of the plurality of protrusions.

12. The method of claim 9 , wherein the ridge has a height that is in a range of between approximately 5% and approximately 15% larger than heights of the plurality of protrusions.

13. The method of claim 8 , wherein the dry etch forms a damaged region having crystalline defects along outer edges of the plurality of intermediate protrusions and the second etch removes the damaged region.

14. The method of claim 8 , wherein the plurality of protrusions respectively have a height in a range of between approximately 400 nm and approximately 600 nm.

15. A method of forming an integrated chip, comprising:

forming an image sensing element within a substrate;

performing a wet etching process to form surfaces of the substrate that define a plurality of protrusions; and

wherein the surfaces of the substrate define a first one of the plurality of protrusions having a first segment, wherein an imaginary line extending along the first segment intersects an opposing sidewall of the first one of the plurality of protrusions.

16. The method of claim 15 , wherein the wet etching process exposes the substrate to tetramethylammonium hydroxide (TMAH).

17. The method of claim 15 ,

wherein the substrate comprises a base substrate and an epitaxial layer over the base substrate; and

wherein the wet etching process forms the surfaces of the substrate that define the plurality of protrusions within the epitaxial layer.

18. The method of claim 15 , further comprising:

forming a dielectric material within recesses between the plurality of protrusions.

19. The method of claim 18 , further comprising:

performing a planarization process to remove part of the dielectric material from over the plurality of protrusions.

20. The method of claim 15 , further comprising:

forming a masking layer over the substrate;

performing a dry etching process to etch the substrate according to the masking layer and define a plurality of intermediate protrusions;

removing the masking layer after defining the plurality of intermediate protrusions; and

performing the wet etching process on the plurality of intermediate protrusions to form the plurality of protrusions.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2024
From: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
To: PARABELLUM STRATEGIC OPPORTUNITIES FUND LLC
Reel/Frame 068326/0474 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 25, 2019
From: SU, CHING-CHUNG; HSU, HUNG-WEN; LU, JIECH-FUN; CHOU, SHIH-PEI
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 051101/0798 →
Continuity (4)
Continuation 16420576 · May 23, 2019
Continuation 16190608 · Nov 14, 2018
Division 15597452 · May 17, 2017
Related Publication 20200091223A1 · Mar 19, 2020
Cited By (1)
US 12,484,325