MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE

1 . A method of manufacturing a semiconductor device, comprising

providing a semiconductor die;

surrounding a sidewall of the semiconductor die with a dielectric material;

forming a post passivation interconnect (PPI) over the semiconductor die and electrically coupling the PPI with the semiconductor die;

molding the semiconductor die and the PPI into an integrated semiconductor package;

covering at least a portion of an outer surface of the integrated semiconductor package with a conductive layer, wherein the conductive layer is conformal to the morphology of the portion of the outer surface; and

forming a conductive path inside the integrated semiconductor package electrically coupled to the conductive layer and a ground terminal of the integrated semiconductor package.

2 . The method of claim 1 , wherein the covering of at least the portion of the outer surface of the integrated semiconductor package with the conductive layer includes a vapor deposition operation.

3 . The method of claim 1 , further comprising disposing an electronic component over the PPI, wherein the electronic component is electrically coupled to the semiconductor die through the PPI.

4 . The method of claim 1 , further comprising forming a conductive trace in the dielectric material, wherein the conductive trace is substantially perpendicular to the sidewall.

5 . The method of claim 1 , further comprising:

providing a substrate;

disposing a plurality of semiconductor dies on the substrate;

performing a wafer level package operation to form a plurality of integrated semiconductor packages; and

performing a multi-staged cleaving operation to singulate the plurality of integrated semiconductor packages.

6 . A method of manufacturing a semiconductor device, comprising

providing a substrate;

forming a first section of a conductive post over the substrate;

disposing a semiconductor die over the substrate;

forming a first dielectric layer to surround a sidewall of the semiconductor die, wherein a top surface of the first dielectric layer is lower than a top surface of the semiconductor die;

forming a second section of the conductive post coupled to the first section over the top surface of the first dielectric layer;

forming a third section of the conductive post coupled to the second section; and

forming a second dielectric layer to surround the sidewall of the semiconductor die.

7 . The method of claim 6 , wherein the first section of the conductive post and the third section of the conductive post are extended along a direction perpendicular to a surface of the substrate.

8 . The method of claim 7 , wherein the second section of the conductive post is extended along a direction parallel with the surface of the substrate.

9 . The method of claim 6 , wherein the first section of the conductive post and the third section of the conductive post are between the semiconductor die and the second section of the conductive post.

10 . The method of claim 6 , wherein the first section, the second section and the third section of the conductive post are separated from the semiconductor die.

11 . The method of claim 6 , further comprising:

forming a patterned layer comprising an opening over the substrate; and

filling the opening with a conductive material,

wherein the first section of the conductive post is formed on the conductive material.

12 . The method of claim 6 , wherein the first dielectric layer and the second dielectric layer comprise a same material.

13 . The method of claim 6 , wherein a top surface of the second dielectric layer is aligned with a top surface of the third section of the conductive post and the top surface of the semiconductor die.

14 . A method of manufacturing a semiconductor device, comprising

providing a substrate;

forming a ground terminal over the substrate;

forming a plurality of conductive posts over the substrate;

disposing a semiconductor die over the substrate;

surrounding a sidewall of the semiconductor die with a first molding;

forming a conductive trace coupled to one of the conductive posts;

disposing a second molding over the conductive trace;

performing a multi-staged cleaving operation to singulate an integrated semiconductor package; and

forming an electric magnetic interference (EMI) shield.

15 . The method of claim 14 , further comprising disposing an electronic component over the semiconductor die, the conductive trace and the first molding, wherein the second molding surrounds sidewalls of the electronic component.

16 . The method of claim 14 , wherein the multi-staged cleaving operation comprises:

performing a coarse cut to make a first cleave penetrating the second molding to expose the first molding; and

performing a fine cut to make a second cleave penetrating the first molding,

wherein a width of the first cleave is greater than a width of the second cleave, and the second molding has a tapered sidewall after the multi-staged cleaving operation.

17 . The method of claim 16 , wherein the EMI shield covers a top surface and the tapered sidewall of the second molding, a sidewall of the first molding and a sidewall of the conductive trace.

18 . The method of claim 14 , wherein the multi-staged cleaving operation comprises:

performing a coarse cut to make a first cleave penetrating the first molding to expose the second molding; and

performing a fine cut to make a second cleave penetrating the second molding,

wherein a width of the first cleave is greater than a width of the second cleave, and the first molding has a tapered sidewall after the multi-staged cleaving operation.

19 . The method of claim 18 , wherein the EMI shield covers a top surface and a sidewall of the second molding, the tapered sidewall of the first molding and a sidewall of the conductive trace.

20 . The method of claim 14 , wherein the EMI shield is coupled to the ground terminal through the conductive trace and one of the conductive posts.