Bump structures for semiconductor package

1. A package structure, comprising a first device bonded to a second device, wherein

the first device comprises:

a metal pad overlying a first region of the first device;

an active bump structure overlying the metal pad and comprising a first metal pillar of a first lateral dimension (W 1 );

a passivation layer overlying a second region of the first device, wherein the active bump structure extends above the passivation layer and further wherein the first metal pillar has a topmost surface that is at a first height above a topmost surface of the passivation layer, and

a dummy bump structure directly on the passivation layer in the second region and comprising a second metal pillar of a second lateral dimension (W 2 ), wherein the second metal pillar has a topmost surface that is at the first height above the topmost surface of the passivation layer, wherein the passivation layer electrically and physically isolates the dummy bump structure from any underlying conductors;

the second device comprising a first connector of a third lateral dimension (W 3 ) and a second connector of a fourth lateral dimension (W 4 ), wherein W 3 is greater than or equal to W 4 and wherein W 3 is greater than W 2 ; and

wherein the first metal pillar is solder jointed to the first connector, the second metal pillar is solder jointed to the second connector; and W 1 is equal to W 2 .

2. The package structure of claim 1 , wherein W 3 is greater than W 4 .

3. The package structure of claim 2 , wherein W 2 is equal to W 4 .

4. The package structure of claim 1 , wherein W 1 is equal to W 4 .

5. The package structure of claim 1 , wherein the first device comprises a semiconductor substrate, and the second metal pillar comprises a copper pillar.

6. The package structure of claim 1 , wherein the first connector comprises a copper pillar, and the second connector comprises a copper pillar.

7. The package structure of claim 1 , further comprising a conductive via passing through the second device and electrically connected to the first connector.

8. A package structure, comprising:

a first device having a first region and a second region and comprising a metal pad overlying the first device in the first region, a first metal pillar having a first lateral dimension (W 1 ) overlying and electrically connected to the metal pad, a passivation layer having a top surface and overlying the first device in the second region, and a second metal pillar having a second lateral dimension (W 2 ), the second metal pillar being directly on the passivation layer in the second region and electrically and physically isolated from underlying features by the passivation layer, wherein the first metal pillar and the second metal pillar extend above the top surface of the passivation layer and have respective topmost surfaces that are substantially coplanar with one another; and

a second device having a first side and a second side opposite to the first side and comprising a first connector having a third dimension (W 3 ) and a second connector having a fourth lateral dimension (W 4 ) on the first side,

wherein the first device is bonded to the first side of the second device, in which a first solder joint region is formed between the first metal pillar and the first connector, and a second solder joint region is formed between the second metal pillar and the second connector; and

wherein the lateral dimensions W 1 , W 2 , W 3 and W 4 satisfy the formula: W 1 =W 2 , and W 3 >W 1 .

9. The package structure of claim 8 , wherein the lateral dimensions W 1 , W 2 , W 3 and W 4 satisfies the formula: W 3 >W 4 >W 1 .

10. The package structure of claim 8 , wherein the lateral dimensions W 1 , W 2 , W 3 and W 4 satisfies the formula: W 3 =W 4 .

11. The package structure of claim 8 , further comprising a conductive via passing through a substrate of the second device and electrically connected to the first connector.

12. A method of forming bump structures on a first region and a second region of a semiconductor substrate, comprising:

forming a metal pad overlying the first region of semiconductor substrate;

forming a passivation layer overlying the metal pad and the semiconductor substrate in the first region and the second region;

patterning the passivation layer to expose a portion of the metal pad;

forming an under-bump metallization (UBM) layer on the passivation layer and the exposed portion of the metal pad;

forming a first metal pillar on the UBM layer over the exposed portion of the metal pad and extending through the passivation layer, the first metal pillar having a lateral dimension of W 1 ;

forming a second metal pillar on the UBM layer directly on the passivation layer in the second region;

solder joining the first metal pillar to a third metal pillar, the third metal pillar having a lateral dimension of W 3 ; and

solder joining the second metal pillar to a fourth metal pillar, the fourth metal pillar having a lateral dimension of W 4 ;

wherein the lateral dimension of the first, second, third and fourth metal pillars satisfy the formula: W 1 =W 2 , and W 3 >W 1 .

13. The method of claim 12 , further comprising:

forming a first solder capping layer overlying the first metal pillar; and

forming a second solder capping layer overlying the second metal pillar.