Semiconductor device having a liner layer with a configured profile and method of fabricating thereof

1. A method comprising:

forming a source/drain feature in a semiconductor substrate;

forming an opening in a first layer over the semiconductor substrate, wherein the opening has a first sidewall, a second sidewall, and a bottom, and wherein the opening overlies the source/drain feature;

performing a first deposition process to form a liner layer of material of a first composition on the first sidewall and second sidewall and the bottom;

forming a masking layer in the opening over the liner layer;

etching a first portion of the liner layer while using the masking layer to protect a second portion of the liner layer;

removing the masking layer to expose the second portion of the liner layer wherein the exposing the second portion includes expose a surface of the second portion of the liner layer extending from the first sidewall to the second sidewall;

performing a second deposition process to deposit material of the first composition over the second portion of the liner layer including the exposed surface and on the first sidewall and second sidewall of the opening; and

after performing the second deposition process, filling the opening with a conductive material.

2. The method of claim 1 , wherein the first deposition process includes forming the liner layer of material of the first composition overlying a second composition, wherein the second composition is different than the first composition.

3. The method of claim 1 , wherein the first composition is TiN.

4. The method of claim 1 , further comprising:

after removing the masking layer and before performing the second deposition process, performing another etching to remove a region of the second portion of the liner layer disposed on the first sidewall of the opening.

5. The method of claim 4 , wherein the another etching does not remove the second portion of the liner layer from the bottom of the opening.

6. The method of claim 4 , further comprising:

performing a directional plasma treatment on the liner layer after the first deposition process.

7. The method of claim 6 , wherein the directional plasma treatment alters an etching rate of the first portion and a region of the second portion of the liner layer.

8. The method of claim 1 , further comprising:

forming an interconnect line interfacing a top surface of the conductive material.

9. The method of claim 1 , wherein a silicide region is disposed on the source/drain feature in the semiconductor substrate.

10. A method comprising:

providing a substrate having a gate structure and a source/drain region;

depositing a dielectric layer over the substrate, the gate structure, and the source/drain region;

etching a first opening in the dielectric layer exposing a top surface of the gate structure and a second opening in the dielectric layer exposing a top surface of the source/drain region;

depositing a first portion of a liner layer in the first opening and the second opening;

removing a top region of the first portion of the liner layer from the first opening and the second opening, wherein the top region interfaces a top portion of a sidewall of the first opening and the second opening; and

depositing a second portion of the liner layer after removing the top region, wherein the first and second portions of the liner layer provide a first thickness on the top portion of the sidewalls of the first opening and the second opening and a second thickness on a bottom of the first opening and the second opening, the second thickness being greater than the first thickness.

11. The method of claim 10 , further comprising:

filling the first opening and the second opening with a conductive material over the liner layer.

12. The method of claim 10 , wherein the removing the top region of the first portion of the liner layer includes:

depositing a masking element to protect a bottom region of the first portion of the liner layer, wherein the bottom region is disposed on a sidewall of the first opening and the second opening respectively below the top region.

13. The method of claim 12 , further comprising:

removing the masking element prior to depositing the second portion; and

removing a top region of the first portion of the liner layer from the first opening and the second opening, wherein the top region interfaces a top portion of sidewall of the first opening and the second opening.

14. The method of claim 13 , further comprising:

after the removing the masking element, etching the bottom region of the first portion.

15. A method of fabricating a semiconductor device, comprising:

providing a gate structure and a source/drain region adjacent the gate structure; and

forming a first contact structure interfacing the gate structure, wherein the forming the first contact structure includes:

providing a contact opening;

forming a liner layer having a first thickness at an upper portion of the contact opening and a second thickness at a bottom portion of the contact opening, wherein the second thickness is greater than the first thickness; and

filling the contact opening with a conductive fill layer deposited over the liner layer.

16. The method of claim 15 , wherein the contact opening exposes a top surface of a gate structure.

17. The method of claim 15 , wherein the contact opening exposes a top surface of a source/drain region.

18. The method of claim 17 , further comprising:

performing a silicidation of the exposed top surface of the source/drain region after providing the contact opening and before forming the liner layer.

19. The method of claim 15 , wherein the forming the liner layer includes depositing titanium.

20. The method of claim 19 , wherein the forming the liner layer includes depositing a titanium nitride.