IP Library Granted Patent US 8,728,892
Granted Patent B2
US 8,728,892 · App. 13/101,890 · Granted May 20, 2014

Adaptive fin design for FinFETs

Inventors: Tsong-Hua Ou (Taipei, TW); Shu-Min Chen (Yongkang, TW); Pin-Dai Sue (Tainan, TW); Li-Chun Tien (Tainan, TW); Ru-Gun Liu (Hsin-Chu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
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Quick Facts
Patent No.
US 8,728,892
App. No.
13/101,890
Granted
May 20, 2014
Kind
B2
Abstract

A method of designing a standard cell includes determining a minimum fin pitch of semiconductor fins in the standard cell, wherein the semiconductor fins are portions of FinFETs; and determining a minimum metal pitch of metal lines in a bottom metal layer over the standard cell, wherein the minimum metal pitch is greater than the minimum fin pitch. The standard cell is placed in an integrated circuit and implemented on a semiconductor wafer.

Claims (21)

1. A method comprising:

designing a standard cell comprising:

determining a fin pitch of semiconductor fins in the standard cell, wherein the semiconductor fins are portions of FinFETs, and wherein the fin pitch is equal to or smaller than all other pitches of the semiconductor fins in the standard cell;

determining a grid comprising grid lines having a uniform pitch;

determining a metal pitch of metal lines in a bottom metal layer over the standard cell to be equal to the uniform pitch, wherein the metal pitch is greater than the fin pitch, and wherein the steps of determining the fin pitch and determining the metal pitch are formula based, and are based on formula: (TN*MetP)/FP=FN, wherein TN is a metal track number of the standard cell, MetP is the metal pitch, FP is the fin pitch, and FN is a total number of semiconductor fins that can be accommodated by the standard cell; and

aligning the metal lines to the grid lines, with neighboring metal lines having pitches equal to positive integer times the uniform pitch, wherein the metal lines are in the bottom metal layer of the standard cell; and

implementing the standard cell on a semiconductor wafer.

2. The method of claim 1 , wherein the implementing the standard cell on the semiconductor wafer comprises:

forming mandrels over a semiconductor substrate of the semiconductor wafer;

forming a plurality of semiconductor fins by etching the semiconductor substrate based on patterns of the mandrels, wherein the plurality of semiconductor fins are portions of the semiconductor substrate, and wherein the plurality of semiconductor fins have the fin pitch; and

forming plurality of metal lines over the plurality of semiconductor fins, wherein the plurality of metal lines have the metal pitch.

3. The method of claim 2 , wherein the mandrels comprise a first mandrel in the standard cell and having a first width, and a second mandrel in the standard cell and having a second width greater than the first width, and wherein the second mandrel is a boundary mandrel crossing a boundary of the standard cell.

4. The method of claim 3 , wherein all internal ones of the mandrels inside the standard cell have the first width.

5. The method of claim 2 , wherein none of the mandrels cross boundaries of the standard cell.

6. The method of claim 1 , wherein the standard cell has a cell height equal to an integer times the metal pitch.

7. The method of claim 1 , wherein the standard cell has a cell height equal to an integer times the metal pitch plus a half of the fin pitch.

8. The method of claim 1 further comprising, before the step of forming the standard cell, designing the standard cell comprising:

designing the semiconductor fins having an additional fin pitch different from the fin pitch;

determining a performance of the standard cell; and

based on a result of the performance failing to meet design specification, re-designing the semiconductor fins to have the fin pitch.

9. The method of claim 1 , wherein the positive integer is greater than 1.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2024
From: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
To: PARABELLUM STRATEGIC OPPORTUNITIES FUND LLC
Reel/Frame 068326/0474 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2011
From: OU, TSONG-HUA; CHEN, SHU-MIN; SUE, PIN-DAI; TIEN, LI-CHUN; LIU, RU-GUN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 026621/0439 →
Continuity (1)
Related Publication 20120280331A1 · Nov 8, 2012