Semiconductor device
A semiconductor device includes a semiconductor substrate, a gate electrode, a source/drain contact, a conductive structure, and a dielectric liner. The semiconductor substrate has a channel region and a source/drain region. The gate electrode is over the channel region. The source/drain contact is over the source/drain region. The conductive structure is over a top surface of the source/drain contact. The dielectric liner surrounds the conductive structure and is over the top surface of the source/drain contact.
1. A semiconductor device, comprising:
a semiconductor substrate having a channel region and a source/drain region;
a gate structure over the channel region;
a gate spacer formed on a sidewall surface of the gate structure;
a source/drain contact over the source/drain region;
an interlayer dielectric layer formed over the substrate;
a conductive structure formed in the interlayer dielectric layer and over a top surface of the source/drain contact;
a dielectric liner disposed between the conductive structure and the interlayer dielectric layer and separating sidewall surfaces of the conductive structure from the interlayer dielectric layer, wherein a bottom surface of the dielectric liner is below a top surface of the gate spacer;
a gate contact structure extending upwardly from the gate structure;
a second dielectric layer over the interlayer dielectric layer, wherein a top surface of the dielectric liner is below a bottom surface of the second dielectric layer; and
wherein the gate contact structure extends through the second dielectric layer.
2. The semiconductor device of claim 1 wherein the structure comprises a gate electrode, and wherein the dielectric liner contacts the gate spacer.
3. The semiconductor device of claim 1 wherein the gate contact structure is electrically isolated from the conductive structure by the dielectric liner and the interlayer dielectric layer.
4. The semiconductor device of claim 1 wherein an interface between the dielectric liner and the source/drain contact is lower than the top surface of the gate spacer.
5. The semiconductor device of claim 1 wherein top surfaces of the conductive structure, the interlayer dielectric layer and the conductive structure are co-planar.
6. The semiconductor device of claim 1 wherein the source/drain region comprises one or more epitaxial layers.
7. The semiconductor device of claim 6 wherein the one or more epitaxial layers comprise silicon.
8. The semiconductor device of claim 6 wherein the one or more epitaxial layers comprise silicon germanium.
9. The semiconductor device of claim 1 wherein the substrate comprises a fin and wherein the source/drain region is formed in the fin.
10. The semiconductor device of claim 1 wherein the dielectric liner contacts the gate spacer.
11. The semiconductor device of claim 1 wherein a bottom end of the dielectric liner and a bottom surface of the conductive structure are in contact with the source/drain contact.
12. The semiconductor device of claim 1 wherein the gate contact structure is formed by two or more processes.