Memory device and method of fabricating the memory device
The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The method for forming a semiconductor structure includes forming a semiconductor stack over a substrate, wherein the semiconductor stack includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatively stacked, patterning the semiconductor stack to form a first fin and a second fin adjacent to the first fin, and removing the second semiconductor layers to obtain a first group of nanosheets over the first fin and a second group of nanosheets over the second fin, wherein a lateral spacing between one of the nanosheets in the first group and a corresponding nanosheet in the second group is smaller than a vertical spacing between each of the nanosheets in the first group.
1. A method for fabricating a semiconductor structure, comprising:
forming a semiconductor stack over a substrate, wherein the semiconductor stack comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatively stacked;
patterning the semiconductor stack to form a first fin and a second fin adjacent to the first fin; and
removing the second semiconductor layers to obtain a first group of nanosheets over the first fin and a second group of nanosheets over the second fin,
wherein a lateral spacing between one of the nanosheets in the first group and a corresponding nanosheet in the second group is smaller than a vertical spacing between each of the nanosheets in the first group.
2. The method of claim 1 , further comprising forming a ferroelectric layer surrounding each of the nanosheets in the first group and each of the nanosheets in the second group by an atomic layer deposition (ALD) operation.
3. The method of claim 1 , further comprising forming a first metal gate layer at least partially surrounding each of the nanosheets in the first group.
4. The method of claim 3 , further comprising forming a second metal gate layer surrounding each of the nanosheets in the second group, wherein the first metal gate layer is in direct contact with the second metal gate layer.
5. The method of claim 1 , further comprising removing a portion of the nanosheets in the first group.
6. The method of claim 2 , wherein forming the ferroelectric layer comprises in-situ doping zirconium or silicon in a hafnium oxide layer.
7. A method for fabricating a semiconductor structure, comprising:
forming a first semiconductor nanosheet over a first region of a substrate;
forming a second semiconductor nanosheet over a second region of the substrate, wherein the second region is adjacent to the first region; and
forming a first ferroelectric layer at least partially surrounding the first semiconductor nanosheet.
8. The method of claim 7 , wherein the second semiconductor nanosheet is at least partially surrounded by the first ferroelectric layer.
9. The method of claim 7 , wherein forming the first ferroelectric layer comprises performing an atomic layer deposition (ALD) operation.
10. The method of claim 7 , wherein forming the first ferroelectric layer comprises in-situ doping zirconium in a hafnium oxide layer.
11. The method of claim 7 , wherein forming the first ferroelectric layer comprises in-situ doping silicon in a hafnium oxide layer.
12. The method of claim 7 , further comprising forming a first metal gate layer at least partially surrounding the first ferroelectric layer.
13. A method for fabricating a semiconductor structure, comprising:
forming a first group of nanosheets at a first level above a substrate, wherein the first group of nanosheets comprises:
a first semiconductor nanosheet; and
a second semiconductor nanosheet adjacent to the first semiconductor nanosheet;
forming a second group of nanosheets at a second level above the first level, wherein the second group of nanosheets comprises:
a third semiconductor nanosheet above the first semiconductor nanosheet; and
a fourth semiconductor nanosheet above the second semiconductor nanosheet;
removing the third semiconductor nanosheet; and
forming a conductive via at a position directly above the first semiconductor nanosheet.
14. The method of claim 13 , further comprising forming a first ferroelectric layer at least partially surrounding the first semiconductor nanosheet prior to forming the conductive via.
15. The method of claim 13 , further comprising forming a first metal gate layer at least partially surrounding the first semiconductor nanosheet prior to forming the conductive via.
16. The method of claim 14 , wherein forming the first ferroelectric layer comprises in-situ doping zirconium or silicon in a hafnium oxide layer.
17. The method of claim 14 , wherein the third semiconductor nanosheet is removed subsequent to forming the first ferroelectric layer.
18. The method of claim 14 , wherein forming the first ferroelectric layer comprises performing an atomic layer deposition (ALD) operation.
19. The method of claim 13 , further comprising forming a first epitaxial feature connected to a first side of the second semiconductor nanosheet.
20. The method of claim 19 , further comprising forming a second epitaxial feature connected to a second side of the second semiconductor nanosheet, wherein the second side is opposite to the first side.