IP Library Granted Patent US 9,293,442
Granted Patent B2
US 9,293,442 · App. 14/276,784 · Granted Mar 22, 2016

Semiconductor package and method

Inventors: An-Jhih Su (Bade, TW); Hsien-Wei Chen (Hsin-Chu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L25/0657H01L24/17H01L24/19H01L24/20H01L24/69H01L24/81H01L25/105H01L2224/0401H01L2224/04105H01L2224/12105H01L2224/1703H01L2225/1035H01L2225/1041H01L2225/1058H01L2924/12042H01L2924/15311H01L2924/181H01L2924/3511
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Quick Facts
Patent No.
US 9,293,442
App. No.
14/276,784
Granted
Mar 22, 2016
Kind
B2
Abstract

A first package is bonded to a second package with a structural member located between the first package and the second package for structural support. In an embodiment the structural member is a plate or one or more conductive balls. Once the structural member is in place, the first package is bonded to the second package.

Claims (31)

1. A semiconductor device comprising:

a first package with a first side;

a second package with a second side facing the first side;

first external connections electrically connecting the first side of the first package and the second side of the second package; and

a structural member between the first package and the second package, wherein the structural member has a different dimension than the first external connections, wherein the structural member is not in contact with a contact pad of the first package.

2. The semiconductor device of claim 1 , wherein the structural member is a block.

3. The semiconductor device of claim 2 , wherein the block is a copper block.

4. The semiconductor device of claim 1 , wherein the structural member is a first solid ball.

5. The semiconductor device of claim 4 , wherein the first solid ball is a solder ball.

6. The semiconductor device of claim 4 , wherein the first external connections comprise a second solid ball, the second solid ball having a larger dimension than the first solid ball.

7. The semiconductor device of claim 1 , wherein the second package is an integrated fan out package.

8. A semiconductor device comprising:

a first package with a first side, the first package comprising a first semiconductor device;

first external connections connected to the first side;

a support member adjacent to the first side, the support member surrounded by the first external connections, wherein the support member is electrically isolated from the first semiconductor device; and

a second package with a second side facing the first side, the second side connected to the first external connections.

9. The semiconductor device of claim 8 , wherein the support member is a block.

10. The semiconductor device of claim 9 , wherein the block is a metal block.

11. The semiconductor device of claim 8 , wherein the support member is one or more solid balls.

12. The semiconductor device of claim 11 , wherein the one or more solid balls are solder balls.

13. The semiconductor device of claim 11 , wherein the first external connections are balls, and wherein the one or more solid balls are smaller than the first external connections.

14. The semiconductor device of claim 8 , wherein the second package is an integrated fan out package.

15. A method of manufacturing a semiconductor device, the method comprising:

forming a first external connection on a first side of a first package;

placing a structural member on the first side of the first package, wherein the structural member has a different dimension than the first external connection; and

bonding the first package to a second package such that the structural member is between the first package and the second package.

16. The method of claim 15 , wherein the first package is an integrated fan out package.

17. The method of claim 15 , wherein the placing the structural member places a metal block.

18. The method of claim 15 , wherein the placing the structural member places one or more solid balls.

19. The method of claim 18 , wherein the one or more solid balls have a smaller diameter than the first external connection.

20. The semiconductor device of claim 1 , wherein the second package is an integrated fan out package.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2024
From: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
To: PARABELLUM STRATEGIC OPPORTUNITIES FUND LLC
Reel/Frame 068326/0474 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2014
From: SU, AN-JHIH; CHEN, HSIEN-WEI
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
Reel/Frame 032882/0528 →
Continuity (2)
Provisional Application 61949755 · Mar 7, 2014
Related Publication 20150255431A1 · Sep 10, 2015