Method of manufacturing a semiconductor device with separated merged source/drain structure
In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. A mask pattern is formed over the sacrificial layer. The sacrificial layer and the source/drain structure are patterned by using the mask pattern as an etching mask, thereby forming openings adjacent to the patterned sacrificial layer and source/drain structure. A dielectric layer is formed in the openings. After the dielectric layer is formed, the patterned sacrificial layer is removed to form a contact opening over the patterned source/drain structure. A conductive layer is formed in the contact opening.
1. A method of forming a semiconductor device including a fin field effect transistor (FinFET) of a first conductivity type, the method comprising:
forming a sacrificial layer over a source/drain structure of a FinFET structure and an isolation insulating layer;
forming a mask pattern over the sacrificial layer;
patterning the sacrificial layer and the source/drain structure by using the mask pattern as an etching mask, thereby forming openings adjacent to sides of the patterned sacrificial layer and sides of the patterned source/drain structure, and reducing a width of the source/drain structure;
forming a dielectric layer in the openings;
after the dielectric layer is formed, removing the patterned sacrificial layer to form a contact opening directly over the patterned source/drain structure; and
forming a conductive layer in the contact opening.
2. The method of claim 1 , wherein before the sacrificial layer is formed, a first insulating layer is formed over the source/drain structure and the isolation insulating layer.
3. The method of claim 1 , wherein the sacrificial layer is made of one or more of Group IV elemental or compound materials.
4. The method of claim 1 , wherein the sacrificial layer is made of one or more of silicon based or aluminum based dielectric material.
5. The method of claim 2 , further comprising, after the sacrificial layer and the source/drain structure are patterned and before the dielectric layer is formed:
forming a second insulating layer over the patterned sacrificial layer and source/drain structure.
6. The method of claim 5 , further comprising, after the sacrificial layer and the source/drain structure are patterned and before the second insulating layer is formed:
forming a silicide layer over the patterned source/drain structure.
7. The method of claim 5 , wherein the sacrificial layer is made of a different material than the isolation insulating layer, the first insulating layer and the second insulating layer.
8. The method of claim 1 , wherein:
the source/drain structure includes a fin structure and one or more epitaxial layers formed on both opposing side faces and a top of the fin structure, and
the source/drain structure is patterned such that the one or more epitaxial layers formed on at least one of the side faces are partially etched.
9. The method of claim 8 , wherein the source/drain structure is patterned such that the one or more epitaxial layers formed on both of the side faces are partially etched.
10. The method of claim 1 , wherein:
the source/drain structure includes a fin structure embedded in the isolation insulating layer and one or more epitaxial layers formed on a top of the fin structure, and
the source/drain structure is patterned such that the one or more epitaxial layers are partially etched.
11. The method of claim 1 , wherein:
the fin structure is protruding from an isolation insulating layer, and
after the sacrificial layer and the source/drain structure are patterned, a surface of the isolation insulating layer is exposed.
12. A method of forming a semiconductor device including fin field effect transistors (FinFETs), the method comprising:
forming a sacrificial layer over a first source/drain structure of a first FinFET structure, a second source/drain structure of a second FinFET structure and an isolation insulating layer, the first source/drain structure and the second source/drain structure being merged;
forming a mask pattern over the sacrificial layer;
patterning the sacrificial layer and the first and second source/drain structures by using the mask pattern as an etching mask, thereby separating the first and second source/drain structures, which are merged before separating, and forming openings adjacent to the patterned sacrificial layer and the patterned first and second source/drain structures;
forming a dielectric layer in the openings;
after the dielectric layer is formed, removing the patterned sacrificial layer to form contact openings over the patterned first and second source/drain structures, respectively; and
forming conductive layers in the contact openings,
wherein before the sacrificial layer is formed, a first insulating layer is formed over the merged first and second source/drain structures and the isolation insulating layer.
13. The method of claim 12 , wherein the first source/drain structure has a same conductivity type as the second source/drain structure.
14. The method of claim 12 , wherein the first source/drain structure has a different conductivity type than the second source/drain structure.
15. The method of claim 12 , wherein the sacrificial layer is made of at least one of Si, SiGe and Ge.
16. The method of claim 12 , wherein the sacrificial layer is made of at least one of SiOC, SiC, SiON, SiCN, SiOCN, SiN and SiO 2 .
17. The method of claim 12 , further comprising, after the sacrificial layer and the first and second source/drain structures are patterned and before the dielectric layer is formed:
forming a second insulating layer over the patterned sacrificial layer and first and second source/drain structures.
18. The method of claim 17 , wherein the sacrificial layer is made of a different material than the isolation insulating layer, the first insulating layer and the second insulating layer.
19. The method of claim 12 , wherein:
the first source/drain structure includes a first epitaxial layer, and the second source/drain structure includes a second epitaxial layer,
the first epitaxial layer is merged with the second epitaxial layer, and
the first and second source/drain structures are patterned such that the merged first and second epitaxial layers are separated.
20. A method of forming a semiconductor device, the method comprising:
forming an epitaxial layer on a source/drain region of a fin structure;
forming a sacrificial layer over the epitaxial layer;
patterning the sacrificial layer and the epitaxial layer such that the patterned sacrificial layer is disposed on an uppermost portion of the patterned epitaxial layer and just above the source/drain region of the fin structure;
forming an insulating layer over the patterned sacrificial layer and the patterned epitaxial layer;
forming a dielectric layer over the insulating layer;
after the dielectric layer is formed, removing the patterned sacrificial layer to form a contact opening directly over the patterned epitaxial layer such that the uppermost portion of the patterned epitaxial layer is exposed in the contact opening; and
forming a conductive contact directly over the patterned epitaxial layer by filling the contact opening with a conductive material, wherein:
the source/drain region of the fin structure protrudes from an isolation insulating layer, and
after the sacrificial layer and the epitaxial layer are patterned, a surface of the isolation insulating layer is exposed and a width of the patterned epitaxial layer is reduced.