Structure and method for semiconductor devices

1. A method, comprising:

forming a stack including first semiconductor layers and second semiconductor layers over a semiconductor substrate, wherein the first semiconductor layers and the second semiconductor layers have different material compositions and alternate with one another within the stack;

forming a dummy gate structure over the stack, wherein the dummy gate structure wraps around top and sidewall surfaces of the stack;

forming first spacers on sidewalls of the dummy gate structure, the first spacer being disposed on the top of the stack;

forming a first tapered trench and a second tapered trench in the stack to expose a top surface of the semiconductor substrate;

removing first portions of the second semiconductor layers disposed below the first spacers to form gaps;

forming second spacers in the gaps, wherein the second spacers have a different material composition from the first spacers, wherein forming the second spacers in the gaps includes conformally depositing a first dielectric layer in the gaps and non-conformally depositing a second dielectric layer in the gaps, defining an airgap enclosed by the first and second dielectric layers;

forming a first source/drain feature in the first tapered trench and a second source/drain feature in the second tapered trench;

removing the dummy gate structure from the top and the sidewall surfaces of the stack; and

removing the second semiconductor layers such that the first semiconductor layers remain and form semiconductor sheets connecting the first source/drain feature and the second source/drain feature to each other, wherein a length of a topmost first semiconductor layer is less than a length of a bottommost first semiconductor layer, as measured in a first direction parallel to the top surface of the semiconductor substrate.

2. The method of claim 1 , wherein forming the first source/drain feature in the first tapered trench and the second source/drain feature in the second tapered trench include a bottom-up epitaxial growth process.

3. The method of claim 1 , wherein forming the first tapered trench and the second tapered trench in the stack includes

applying a first etchant having hydrogen bromide (HBr) combined with argon (Ar), helium (He), oxygen (O 2 ), or a combination thereof; and

applying a second etchant having HBr combined with nitrogen, methane (CH 4 ), or a combination thereof.

4. The method of claim 1 , after removing the second semiconductor layers, further comprising forming a metal gate structure wrapping around each of the first semiconductor layers, wherein the first semiconductor layers are stacked and spaced apart in a second direction perpendicular to the first direction, the second direction being normal to the top surface of the semiconductor substrate.

5. The method of claim 4 , wherein a width of the topmost first semiconductor layer is different from a width of the bottommost first semiconductor layer, wherein each of the width of the topmost first semiconductor layer and the width of the bottommost first semiconductor layer is measured in a third direction perpendicular to the first direction and the second direction.

6. The method of claim 4 , wherein forming the metal gate structure includes forming the metal gate structure that further includes a first portion engaging the topmost first layer semiconductor layer and a second portion engaging the bottommost first semiconductor layer, wherein a length of the first portion of the metal gate structure along the first direction is less than a length of the second portion of the metal gate structure along the first direction.

7. The method of claim 6 , wherein

removing the dummy gate structure includes applying a first etchant having hydrogen bromide (HBr) combined with chlorine (Cl 2 ), tetrafluoromethane (CF 4 ), oxygen, or a combination thereof; and

removing the second semiconductor layers includes applying a second etchant having hydrogen bromide (HBr) combined with chlorine (Cl 2 ), oxygen, or a combination thereof.

8. The method of claim 1 , further comprising:

forming a gate end dielectric layer contacting opposing ends of each of the plurality of first semiconductor layers, wherein

the first spacer includes a first dielectric material having a first dielectric constant;

the second spacer includes a second dielectric material having a second dielectric constant different from the first dielectric constant; and

the gate end dielectric layer includes a third dielectric material having a third dielectric constant, the third dielectric constant being larger than the first dielectric constant and the second dielectric constant.

9. A method, comprising:

forming a stack including first semiconductor layers and second semiconductor layers over a semiconductor substrate, wherein the first semiconductor layers and the second semiconductor layers have different material compositions and alternate with one another within the stack;

forming a dummy gate structure over the stack, wherein the dummy gate structure wraps around top and sidewall surfaces of the stack;

forming first spacers on sidewalls of the dummy gate structure, the first spacer being disposed on the top of the stack;

forming a first tapered trench and a second tapered trench in the stack to expose a top surface of the semiconductor substrate;

forming a first source/drain feature in the first tapered trench and a second source/drain feature in the second tapered trench;

removing the dummy gate structure from the top and the sidewall surfaces of the stack to form a gate trench;

removing the second semiconductor layers to form a tapered gate trench such that the first semiconductor layers remain and form semiconductor sheets connecting the first source/drain feature and the second source/drain feature to each other; and

forming a gate structure wrapping around each of the first semiconductor layers.

10. The method of claim 9 , wherein a first portion of the gate structure engages a topmost first semiconductor layer and a second portion of the gate structure engages a bottommost first semiconductor layer, wherein a length of the first portion of the gate structure along the first direction is less than a length of the second portion of the gate structure along the first direction.

11. The method of claim 9 , wherein

removing the dummy gate structure includes applying a first etchant having hydrogen bromide (HBr) combined with chlorine (Cl 2 ), tetrafluoromethane (CF 4 ), oxygen, or a combination thereof; and

removing the second semiconductor layers includes applying a second etchant having hydrogen bromide (HBr) combined with chlorine (Cl 2 ), oxygen, or a combination thereof.

12. The method of claim 9 , wherein a length of the topmost first semiconductor layer is less than a length of the bottommost first semiconductor layer, as measured in a first direction parallel to the top surface of the semiconductor substrate.

13. The method of claim 12 , wherein a width of the topmost first semiconductor layer is different from a width of the bottommost first semiconductor layer, wherein each of the width of the topmost first semiconductor layer and the width of the bottommost first semiconductor layer is measured in a second direction perpendicular to the first direction and parallel to the top surface of the semiconductor substrate.

14. The method of claim 9 , wherein forming the first source/drain feature in the first tapered trench and the second source/drain feature in the second tapered trench include a bottom-up epitaxial growth process.

15. The method of claim 9 , further comprising:

after forming the first tapered trench and the second tapered trench, removing first portions of the second semiconductor layers disposed below the first spacers to form gaps; and

forming second spacers in the gaps, the second spacers have a different material composition from the first spacers.

16. The method of claim 15 , wherein forming the second spacers in the gaps includes conformally depositing a first dielectric layer in the gaps and non-conformally depositing a second dielectric layer in the gaps, defining an airgap enclosed by the first and second dielectric layers.

17. A method, comprising:

forming a stack including first semiconductor layers and second semiconductor layers over a semiconductor substrate, wherein the first semiconductor layers and the second semiconductor layers have different material compositions and alternate with one another within the stack;

forming a dummy gate structure over the stack, wherein the dummy gate structure wraps around top and sidewall surfaces of the stack;

forming first spacers on sidewalls of the dummy gate structure, the first spacer being disposed on the top of the stack;

forming a first tapered trench and a second tapered trench in the stack to expose a top surface of the semiconductor substrate;

forming a first source/drain feature in the first tapered trench and a second source/drain feature in the second tapered trench;

removing the dummy gate structure from the top and the sidewall surfaces of the stack; and

removing the second semiconductor layers such that the first semiconductor layers remain and form semiconductor sheets connecting the first source/drain feature and the second source/drain feature to each other, wherein a length of a topmost first semiconductor layer is less than a length of a bottommost first semiconductor layer, as measured in a first direction parallel to the top surface of the semiconductor substrate, and wherein a width of the topmost first semiconductor layer is different from a width of the bottommost first semiconductor layer, as measured in a second direction perpendicular to the first direction and parallel to the top surface of the semiconductor substrate.

18. The method of claim 17 , wherein forming the first source/drain feature in the first tapered trench and the second source/drain feature in the second tapered trench include a bottom-up epitaxial growth process.

19. The method of claim 17 , further comprising:

after forming the first tapered trench and the second tapered trench, removing first portions of the second semiconductor layers disposed below the first spacers to form gaps; and

forming second spacers in the gaps, wherein the second spacer includes an air gap.

20. The method of claim 17 , further comprising:

forming a first tapered trench and a second tapered trench in the stack to expose a top surface of the semiconductor substrate;

removing first portions of the second semiconductor layers disposed below the first spacers to form gaps; and

forming second spacers in the gaps, wherein forming the second spacers in the gaps includes conformally depositing a first dielectric layer in the gaps and non-conformally depositing a second dielectric layer in the gaps, defining an airgap enclosed by the first and second dielectric layers.