Gate-all-around structure and methods of forming the same
Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer including different semiconductor materials, and the fin comprises a channel region and a source/drain region; forming a dummy gate structure over the channel region of the fin and over the substrate; etching a portion of the fin in the source/drain region to form a trench therein, wherein a bottom surface of the trench is below a bottom surface of the second semiconductor layer; selectively removing an edge portion of the second semiconductor layer in the channel region such that the second semiconductor layer is recessed; forming a sacrificial structure around the recessed second semiconductor layer and over the bottom surface of the trench; and epitaxially growing a source/drain feature in the source/drain region of the fin.
1. A device comprising:
a fin protruding from a substrate and disposed between portions of an isolation structure;
a semiconductor layer over the fin;
a gate dielectric wrapping around the semiconductor layer;
a gate electrode wrapping around the gate dielectric disposed on the semiconductor layer;
a source/drain feature interfacing with the semiconductor layer; and
a dielectric inner spacer having first portions contacting side surfaces of the source/drain feature and second portions contacting top and bottom surfaces of the source/drain feature; and
an etch stop layer over and in direct contact with the dielectric inner spacer.
2. The device of claim 1 , further comprising an interlayer dielectric (ILD) layer over the etch stop layer.
3. The device of claim 1 , further comprising:
a fin dielectric layer extending from the substrate along a sidewall of the fin, the fin dielectric layer contacting the dielectric inner spacer and the isolation structure.
4. The device of claim 1 , wherein the semiconductor layer is a first semiconductor layer, further comprising:
a second semiconductor layer over the first semiconductor layer,
wherein the first portions of the dielectric inner spacer are disposed vertically between the first and the second semiconductor layers.
5. The device of claim 1 , wherein a top surface of the isolation structure is above a bottommost surface of the dielectric inner spacer.
6. The device of claim 1 , wherein the dielectric inner spacer wraps around the source/drain feature.
7. The device of claim 1 , wherein the semiconductor layer has a first thickness adjacent the source/drain feature and a second thickness positioned further away from the source/drain feature, the second thickness being different than the first thickness.
8. The device of claim 7 , wherein the gate dielectric wraps around a first portion of the semiconductor layer having the second thickness without wrapping around a second portion of the semiconductor layer having the first thickness.
9. A device comprising:
a fin protruding from a substrate and disposed between portions of an isolation structure;
a semiconductor layer over the fin;
a gate dielectric wrapping around the semiconductor layer;
a gate electrode wrapping around the gate dielectric disposed on the semiconductor layer;
a source/drain feature interfacing with the semiconductor layer; and
a dielectric inner spacer having first portions contacting side surfaces of the source/drain feature and a second portion contacting a bottom surface of the source/drain feature; and
an etch stop layer over and in direct contact with the source/drain feature.
10. The device of claim 9 , further comprising an interlayer dielectric (ILD) layer over the etch stop layer.
11. The device of claim 9 , further comprising a fin dielectric layer extending from the substrate along a sidewall of the fin, the fin dielectric layer contacting the dielectric inner spacer and the isolation structure.
12. The device of claim 11 , wherein the fin dielectric layer includes a top portion above a top surface of the isolation structure, and the top portion of the fin dielectric layer is disposed vertically between the source/drain feature and the isolation structure.
13. The device of claim 12 , wherein the etch stop layer, the top portion of the fin dielectric layer, and the second portion of the dielectric inner spacer wrap around the source/drain feature.
14. The device of claim 9 , wherein a top surface of the isolation structure is above a bottommost surface of the dielectric inner spacer.
15. A device comprising:
a fin protruding from a substrate and disposed between portions of an isolation structure;
a semiconductor layer over a first portion of the fin;
a gate dielectric wrapping around the semiconductor layer;
a gate electrode wrapping around the gate dielectric disposed on the semiconductor layer;
a source/drain feature interfacing with the semiconductor layer; and
a dielectric inner spacer layer having a bottom portion disposed between the source/drain feature and the substrate and directly contacting the source/drain feature and the substrate.
16. The device of claim 15 , wherein the dielectric inner spacer has a top portion disposed on top and directly contacting the source/drain feature.
17. The device of claim 15 , wherein the semiconductor layer is a bottommost semiconductor layer of a stack of semiconductor layers, and the bottom portion of the dielectric inner spacer layer directly contacts a bottom surface of the semiconductor layer.
18. The device of claim 16 , wherein the semiconductor layer is a first semiconductor layer, the gate dielectric is a first gate dielectric, and the gate electrode is a first gate electrode, further comprising:
a second semiconductor layer over a second portion of the fin;
a second gate dielectric wrapping around the second semiconductor layer; and
a second electrode wrapping around the second gate dielectric disposed on the second semiconductor layer,
wherein the source/drain feature interfaces with the second semiconductor layer and is disposed between side surfaces of the first and second semiconductor layers.
19. The device of claim 18 , wherein the bottom portion of the dielectric inner spacer layer directly contacts the first and the second semiconductor layers.
20. The device of claim 18 , wherein the top portion of the dielectric inner spacer layer directly contacts the first and the second gate electrodes.