Structure of semiconductor device structure having fins
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.
1 . A method for forming a semiconductor device structure, comprising:
depositing a dielectric layer over a first transistor structure and a second transistor structure;
forming a dummy gate stack extending over the first transistor structure and the second transistor structure;
removing the dummy gate stack to form a trench between the first transistor structure and the second transistor structure, the trench extending over a semiconductor substrate;
forming metal gate stack layers in the trench;
forming at least one recess in the metal gate stack layers to separate the metal gate stack layers into at least two gate stacks, wherein the recess has an upper width and a lower width, and the lower width is greater than the upper width; and
depositing an isolation element in the at least one recess.
2 . The method of claim 1 , further comprising:
forming a first fin structure for the first transistor structure; and
forming a second fin structure for the second transistor structure.
3 . The method of claim 1 , wherein the step of depositing a dielectric layer includes depositing multiple dielectric layers including at least one liner layer.
4 . The method of claim 1 , further comprising:
depositing a second dielectric layer over the dummy gate stack before removing the dummy gate stack; and
thinning the second dielectric layer to expose a top surface of the dummy gate stack.
5 . The method of claim 1 , further comprising forming dummy gate spacers on respective sidewalls of the dummy gate stack, and wherein the dummy gate spacers remain extant after removing the dummy gate stack.
6 . The method of claim 1 , wherein the step of forming metal gate stack layers in the trench includes:
forming an n-type metal gate stack in the first transistor structure; and
forming a p-type metal gate stack in the second transistor structure.
7 . The method of claim 6 , wherein the n-type metal gate stack includes at least one layer also included in the p-type metal gate stack and further includes at least one layer not included in the p-type metal gate stack.
8 . A method comprising:
forming a fin structure over a semiconductor substrate;
covering a portion of the fin structure with a gate stack, wherein the gate stack comprises a work function layer and a metal filling over the work function layer; and
forming an isolation element dividing the gate stack into two regions, wherein the isolation element has a trapezoidal shape when viewed in cross section, the trapezoidal shape being wider at the bottom, nearer the semiconductor substrate, relative to the top.
9 . The method of claim 8 , further comprising covering a portion of a second fin structure with the gate stack.
10 . The method of claim 9 , wherein the gate stack further comprises a second work function layer where it covers the portion of the second fin structure.
11 . The method of claim 8 , wherein the step of forming an isolation element dividing the gate stack into two regions includes:
forming a dummy gate stack over the fin structure;
partially covering the fin structure and the dummy gate stack with a dielectric layer,
removing the dummy gate stack for form a trench in the dielectric layer;
filling the trench with metal layers;
etching into the metal layers to form an opening therein; and
filling the opening with the isolation element.
12 . The method of claim 8 , wherein the step of forming an isolation element 134 ′ dividing the gate stack into two regions includes performing an etching process on the gate stack to form a recess into the gate stack and varying the etching conditions during the etching process.
13 . The method of claim 12 , wherein varying the etching conditions includes varying the composition of etchant gas mixture during the etching process.
14 . The method of claim 11 , wherein the step of filling the opening with the isolation element includes depositing into the opening a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, carbon-containing silicon oxide, and combinations thereof.
15 . A method comprising:
forming a first transistor region in a first fin structure extending from a substrate and a second transistor region in a second fin structure extending from the substrate;
forming a gate stack extending over the first transistor region and the second transistor region;
patterning the gate stack to have an opening extending therethrough, the opening having a first sidewall facing the first transistor region and a second sidewall facing the second transistor region, wherein the first sidewall slopes toward from the first transistor region when going from a topmost surface of the first sidewall to a bottommost surface of the first sidewall, the topmost surface of the first sidewall being the surface farthest from the substrate, and further wherein the second sidewall slopes toward the second transistor region when going from a topmost surface of the second sidewall to a bottommost surface of the second sidewall, the topmost surface of the second sidewall being the surface farthest from the substrate; and
filling the opening with an isolation structure extending from the first sidewall to the second sidewall.
16 . The method of claim 15 further including:
forming a dummy gate structure extending over the first transistor region and the second transistor region;
forming sidewall spacers on respective sides of the dummy gate structure;
removing the dummy gate structure, while leaving the sidewall spacers intact; and
depositing the gate stack in a space left from removing the dummy gate structure.
17 . The method of claim 15 , wherein the step of patterning the gate stack to have an opening 132 extending therethrough includes etching through metal layers of the gate stack using an etching process while varying etching process conditions.
18 . The method of claim 17 , further comprising varying etching process conditions to cause the opening to have an angle of sidewall slope of from about 10 degrees to about 85 degrees.
19 . The method of claim 15 , wherein the step of forming a gate stack extending over the first transistor region and the second transistor region includes depositing a first stack of metal layers over the first transistor region and depositing a second stack of metal layers over the second transistor region.
20 . The method of claim 19 , further comprising depositing at least one metal layer of the first stack of metal layers simultaneously with a metal layer of the second stack of metal layers.