IP Library › Granted Patent US 9,184,100
Granted Patent B2
US 9,184,100 · App. 13/206,533 · Granted Nov 10, 2015

Semiconductor device having strained fin structure and method of making the same

Inventors: Teng-Chun Tsai (Tainan, TW); Chun-Yuan Wu (Yun-Lin County, TW); Chih-Chien Liu (Taipei, TW); Chin-Cheng Chien (Tainan, TW); Chin-Fu Lin (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L21/845H01L21/823821H01L27/0924H01L27/1211H01L29/1054
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Quick Facts
Patent No.
US 9,184,100
App. No.
13/206,533
Granted
Nov 10, 2015
Kind
B2
Abstract

A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.

Claims (18)

1. A method for forming a semiconductor device, comprising:

providing a semiconductor substrate comprising a first active region and a second active region;

forming a semiconductor layer having a first stress on the semiconductor substrate;

performing an ion implantation process to modify the semiconductor layer in the second active region to have a second stress;

patterning the semiconductor layer for forming at least a first fin structure in the first active region, wherein the overall first fin structure has the first stress; and

patterning the semiconductor layer for forming at least a second fin structure in the second active region, wherein the overall second fin structure has the second stress different from the first stress.

2. The method for forming a semiconductor device according to claim 1 , further comprising:

forming a first gate partially overlapping the first fin structure;

forming a second gate partially overlapping the second fin structure;

forming a first source/drain region in the first fin structure at two sides of the first gate; and

forming a second source/drain region in the second fin structure at two sides of the second gate.

3. The method for forming a semiconductor device according to claim 2 , wherein at least one of the first gate and the second gate comprises a metal gate.

4. The method for forming a semiconductor device according to claim 1 , wherein each of the fin structures comprises a silicon-germanium-carbon material denoted as (Si (1-x-y) Ge x C y ), wherein x and y are positive numbers between 0 and 1 respectively.

5. The method for forming a semiconductor device according to claim 4 , wherein the first active region comprises an n-type metal oxide semiconductor transistor (NMOS) region, and the material of the overall first fin structure comprises a ratio of y to x larger than 0.1.

6. The method for forming a semiconductor device according to claim 4 , wherein the second active region comprises a p-type metal oxide semiconductor transistor (PMOS) region, and the material of the overall second fin structure comprises a ratio of y to x smaller than 0.1.

7. The method for forming a semiconductor device according to claim 1 , wherein the ion implantation process is performed after patterning the semiconductor layer.

8. The method for forming a semiconductor device according to claim 1 , wherein the semiconductor layer comprises silicon, silicon-germanium-carbon (Si (1-x-y) Ge x C y ), silicon-carbon (Si (1-y) C y ) or silicon-germanium (Si (1-x) Ge x ), wherein x and y are zero or a positive number between 0 and 1 respectively.

9. The method for forming a semiconductor device according to claim 1 , wherein the semiconductor substrate comprises a silicon-on-insulator (SOI) substrate or a bulk silicon substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2011
From: TSAI, TENG-CHUN; WU, CHUN-YUAN; LIU, CHIH-CHIEN; CHIEN, CHIN-CHENG; LIN, CHIN-FU
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 026724/0050 →
Continuity (1)
Related Publication 20130037886A1 · Feb 14, 2013