Semiconductor device and method of fabricationg the same
A method of fabricating a semiconductor device includes forming first gate patterns on a semiconductor substrate using an etch mask pattern, forming a trench in the semiconductor substrate between the first gate patterns, forming an insulating layer in the trench, such that the insulating layer fills the trench and is disposed on the etch mask pattern, planarizing the insulating layer until a top surface of the etch mask pattern is exposed, etching a portion of the planarized insulating layer to form a device isolation layer in the trench, forming a second gate layer covering the etch mask pattern and disposed on the device isolation pattern, and planarizing the second gate layer until the top surface of the etch mask pattern is exposed, such that a second gate pattern is formed.
1. A method of fabricating a semiconductor device, the method comprising:
forming first gate patterns on a semiconductor substrate using an etch mask pattern;
forming a trench in the semiconductor substrate between the first gate patterns;
forming an insulating layer in the trench, such that the insulating layer fills the trench and is disposed on the etch mask pattern;
planarizing the insulating layer until a top surface of the etch mask pattern is exposed;
etching a portion of the planarized insulating layer to form a device isolation pattern in the trench;
forming a second gate layer covering the etch mask pattern and disposed on the device isolation pattern; and
planarizing the second gate layer until the top surface of the etch mask pattern is exposed, such that a second gate pattern is formed.
2. The method as claimed in claim 1 , further comprising, before forming the first gate patterns:
forming fins vertically protruding from the semiconductor substrate; and
performing a thermal oxidation process on the semiconductor substrate to form a gate insulating layer conformally covering surfaces of the fins.
3. The method as claimed in claim 2 , wherein forming the first gate patterns includes removing fins in a region between adjacent first gate patterns to be formed subsequently.
4. The method as claimed in claim 1 , wherein forming the device isolation layer includes etching the insulating layer until sidewalls of the first gate patterns are completely exposed.
5. The method as claimed in claim 1 , wherein forming the device isolation layer includes etching the insulating layer until portions of sidewalls of the first gate patterns are exposed.
6. The method as claimed in claim 1 , wherein the etch mask pattern includes a material having an etch selectivity with respect to the insulating layer and the second gate pattern.
7. The method as claimed in claim 1 , wherein the etch mask pattern includes silicon nitride (SiN) or silicon oxide (SiO 2 ).
8. The method as claimed in claim 1 , further comprising, after forming the second gate pattern:
recessing a top surface of the second gate pattern;
removing the etch mask pattern to expose top surfaces of the first gate patterns; and
polishing the top surfaces of the first gate patterns and the top surface of the second gate pattern.
9. A method of fabricating a semiconductor device, the method comprising:
forming first gate patterns on a semiconductor substrate using an etch mask pattern;
forming a trench in the semiconductor substrate between the first gate patterns;
forming an insulating layer in the trench, such that the insulating layer fills the trench and cover a top of the etch mask pattern;
planarizing the insulating layer to expose the top surface of the etch mask pattern;
etching a portion of the planarized insulating layer to form a device isolation pattern in the trench;
forming a second gate layer to fill the trench, such that second gate layer is on the device isolation pattern and on the top of the etch mask pattern;
planarizing the second gate layer to expose the top surface of the etch mask pattern, such that a second gate pattern is formed;
removing a portion of the second gate pattern;
removing etch mask pattern, such that a top surface of the first gate pattern is exposed; and
polishing simultaneously the first and second gate patterns to form a uniform flat surface.
10. The method as claimed in claim 9 , wherein removing the portion of the second gate pattern includes removing a portion having a thickness that substantially equals a thickness of the etch mask pattern.
11. The method as claimed in claim 9 , wherein polishing the first and second gate patterns to form the uniform flat surface includes defining the first and second gate patterns as a single conductive electrode crossing a plurality of fins.
12. The method as claimed in claim 11 , wherein, after forming the first gate patterns, the etch mask pattern covers a top surface of only the first gate patterns among the first and second gate patterns.
13. The method as claimed in claim 9 , wherein forming the trench includes separating adjacent first gate patterns, such that every trench is between two adjacent first gate patterns.
14. The method as claimed in claim 13 , wherein forming the second gate layer in the trench includes filling the trench completely with the second gate layer, such that the second gate layer directly contacts and extends along sidewalls of two adjacent first gate patterns.
15. The method as claimed in claim 14 , wherein planarizing the second gate layer and removing a portion of the second gate pattern are performed while the etch mask pattern completely covers a top surface of the first gate pattern.