Method of fabricating FinFETs
The disclosure relates to a method of fabricating a semiconductor device including forming a patterned hardmask layer over a substrate comprising a major surface. The method further includes forming a plurality of first trenches and a plurality of second trenches performed at an electrostatic chuck (ESC) temperature between about 90° C. to 120° C. in the substrate. The plurality of first trenches have a first width and extend downward from the substrate major surface to a first height, and the plurality of second trenches have a second width less than first width and extend downward from the substrate major surface to a second height greater than the first height.
1. A method of making a fin field effect transistor (FinFET) comprising:
forming a plurality of first trenches having a first width and a first depth in a substrate, each first trench of the plurality of first trenches extending downward from a surface of the substrate to a first height, wherein a first space between adjacent first trenches defines a first fin;
forming a plurality of second trenches having a second width and a second depth in the substrate, the second width less than the first width, each second trench of the plurality of second trenches extending downward from the surface of the substrate to a second height greater than the first height, wherein a second space between adjacent second trenches defines a second fin;
forming a first isolation structure partially filling each first trench of the plurality of first trenches; and
forming a second isolation structure partially filling each second trench of the plurality of second trenches, wherein a difference between a height of the first isolation structure and the first depth is substantially equal to a difference between a height of the second isolation structure and the second depth.
2. The method of claim 1 , wherein forming each of the plurality of first and second trenches comprises using a chemical selected from NF 3 , CF 4 , and SF 6 as an etching gas.
3. The method of claim 1 , wherein each of the plurality of first and second trenches are formed under a pressure of about 2 mTorr to 20 mTorr.
4. The method of claim 1 , wherein each of the plurality of first and second trenches are formed under a source power of about 500 W to 1000 W.
5. The method of claim 1 , wherein each of the plurality of first and second trenches are formed under a pulse bias voltage.
6. The method of claim 1 , wherein forming the first and second isolation structure further comprises forming a liner oxide in each of the plurality of first and second trenches.
7. The method of claim 1 , further comprising forming a first gate stack over the first fin, and forming a second gate stack over the second fin.
8. The method of claim 7 , further comprising forming a dielectric layer between the first gate stack and the second gate stack.
9. A method of making a fin field effect transistor (FinFET) comprising:
forming a plurality of first trenches having a first width and a first depth in a substrate, each first trench of the plurality of first trenches extending downward from a surface of the substrate to a first height, wherein a first space between adjacent first trenches defines a first fin;
forming a plurality of second trenches having a second width and a second depth in the substrate, the second width less than the first width, each second trench of the plurality of second trenches extending downward from the surface of the substrate to a second height greater than the first height, wherein a second space between adjacent second trenches defines a second fin;
forming a first isolation structure partially filling each first trench of the plurality of first trenches;
forming a second isolation structure partially filling each second trench of the plurality of second trenches, wherein a difference between a height of the first isolation structure and the first depth is substantially equal to a different between a height of the second isolation structure and the second depth;
forming a first gate electrode over a top surface and sidewalls of the first fin; and
forming a second gate electrode over a top surface and sidewalls of the second fin.
10. The method of claim 9 , wherein forming each of the plurality of first and second trenches comprises using a chemical selected from NF 3 , CF 4 , and SF 6 as an etching gas.
11. The method of claim 9 , wherein each of the plurality of first and second trenches are formed under a pressure of about 2 mTorr to 20 mTorr.
12. The method of claim 9 , wherein each of the plurality of first and second trenches are formed under a source power of about 500 W to 1000 W.
13. The method of claim 9 , wherein each of the plurality of first and second trenches are formed under a pulse bias voltage.
14. The method of claim 9 , wherein forming the first and second isolation structure further comprises forming a liner oxide in each of the plurality of first and second trenches.
15. The method of claim 9 , further comprising forming a dielectric layer between the first gate electrode and the second gate electrode.