Semiconductor structure with source/drain multi-layer structure and method for forming the same

1. A semiconductor structure, comprising:

a gate structure over a fin structure;

a gate spacer over the fin structure and on a sidewall surface of the gate structure; and

a source/drain structure in the fin structure and adjacent to the gate spacer, wherein the source/drain structure comprises:

a first source/drain epitaxial layer in contact with the fin structure; and

a second source/drain epitaxial layer over the first source/drain epitaxial layer, wherein the first source/drain epitaxial layer is connected to a portion of the second source/drain epitaxial layer below a top surface of the fin structure,

wherein a lattice constant of the first source/drain epitaxial layer of the source/drain structure is greater than a lattice constant of the second source/drain epitaxial layer of the source/drain structure.

2. The semiconductor structure as claimed in claim 1 , wherein the second source/drain epitaxial layer of the source/drain structure is separated from the fin structure by the first source/drain epitaxial layer of the source/drain structure.

3. The semiconductor structure as claimed in claim 1 , wherein the first source/drain epitaxial layer of the source/drain structure comprises a silicon epitaxial layer with a first N-type dopant, and the second source/drain epitaxial layer of the source/drain structure comprises a silicon epitaxial layer with a second N-type dopant that is different from the first N-type dopant.

4. The semiconductor structure as claimed in claim 3 , wherein an atomic radius of the first N-type dopant is greater than an atomic radius of the second N-type dopant.

5. The semiconductor structure as claimed in claim 4 , wherein the first N-type dopant is arsenic (As), and the second N-type dopant is phosphorous (P).

6. The semiconductor structure as claimed in claim 1 , wherein a thickness of the second source/drain epitaxial layer of the source/drain structure is one order to three orders of magnitude greater than a thickness of the first source/drain epitaxial layer of the source/drain structure.

7. The semiconductor structure as claimed in claim 1 , further comprising:

a dielectric spacer over the source/drain structure and on a portion of a sidewall surface of the gate spacer; and

a contact plug over the source/drain structure, wherein the contact plug is separated from the gate spacer through the dielectric spacer.

8. The semiconductor structure as claimed in claim 7 , wherein a top surface of the dielectric spacer is positioned between a top surface and a bottom surface of the gate structure.

9. The semiconductor structure as claimed in claim 7 , wherein the dielectric spacer is directly over the second source/drain epitaxial layer.

10. The semiconductor structure as claimed in claim 7 , wherein the dielectric spacer is formed of a material comprising silicon nitride (SiN) and different from the gate spacer.

11. A semiconductor structure, comprising:

a gate structure over a fin structure;

a gate spacer over the fin structure and on a sidewall surface of the gate structure;

a source/drain structure in the fin structure and adjacent to the gate spacer;

a dielectric spacer over the source/drain structure and on a portion of a sidewall surface of the gate spacer;

a contact plug over the source/drain structure and separated from the gate spacer through the dielectric spacer, wherein a top surface of the dielectric spacer is positioned between a top surface and a bottom surface of the gate structure; and

a source/drain silicide layer on the source/drain structure, wherein the source/drain silicide layer is separated from the gate spacer through the dielectric spacer along a longitudinal direction of the fin structure.

12. The semiconductor structure as claimed in claim 11 , wherein the dielectric spacer is formed of a material comprising silicon nitride (SiN) and different from the gate spacer.

13. The semiconductor structure as claimed in claim 11 , wherein the source/drain structure comprises:

a first source/drain epitaxial layer in contact with the fin structure; and

a second source/drain epitaxial layer over the first source/drain epitaxial layer, wherein the first source/drain epitaxial layer is connected to a portion of the second source/drain epitaxial layer below a top surface of the fin structure.

14. The semiconductor structure as claimed in claim 13 , wherein the dielectric spacer is directly over the second source/drain epitaxial layer of the source/drain structure.

15. The semiconductor structure as claimed in claim 13 , wherein the first source/drain epitaxial layer of the source/drain structure comprises a silicon epitaxial structure with a first N-type dopant, and the second source/drain epitaxial layer of the source/drain structure comprises a silicon epitaxial layer with a second N-type dopant that is different from the first N-type dopant.

16. The semiconductor structure as claimed in claim 13 , wherein the first source/drain epitaxial layer of the source/drain structure comprises SiAs, SiCP, SiC, SiP or a combination thereof.

17. A method for forming a semiconductor structure, comprising:

forming a gate structure over a fin structure;

forming a gate spacer over the fin structure and on a sidewall surface of the gate structure;

removing a portion of the fin structure not covered by the gate structure and the gate spacer to form a recess in the fin structure;

epitaxially growing a source/drain structure in the recess;

forming a blocking layer on a top surface of the source/drain structure;

selectively forming a dielectric spacer on a sidewall surface of the gate spacer rather than on the top surface of the source/drain structure, wherein the gate spacer and the dielectric spacer are formed of different materials after forming the source/drain structure; and

removing the blocking layer from the top surface of the source/drain structure.

18. The method for forming a semiconductor structure as claimed in claim 17 , wherein epitaxially growing the source/drain structure in the recess comprises:

epitaxially growing a first source/drain epitaxial layer lining a surface of the fin structure in the recess; and

epitaxially growing a second source/drain epitaxial layer over the first source/drain epitaxial layer and filling the recess.

19. The method for forming a semiconductor structure as claimed in claim 17 , further comprising:

performing a plasma etching process to remove a portion of the dielectric spacer from a top surface of the dielectric spacer.

20. The method for forming a semiconductor structure as claimed in claim 17 , further comprising:

forming an inter-layer dielectric (ILD) structure over the fin structure, the gate structure, the gate spacer, the source/drain structure and the dielectric spacer;

forming a metal gate structure to replace the gate structure; and

forming a contact plug over the source/drain structure.