IP Library › Granted Patent US 8,525,170
Granted Patent B2
US 8,525,170 · App. 12/423,829 · Granted Sep 3, 2013

Thin film transistor and manufacturing method thereof

Inventors: Shunpei Yamazaki (Tokyo, JP); Yuji Egi (Kanagawa, JP); Shinya Sasagawa (Kanagawa, JP); Motomu Kurata (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
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Quick Facts
Patent No.
US 8,525,170
App. No.
12/423,829
Granted
Sep 3, 2013
Kind
B2
Abstract

Off current of a thin film transistor is reduced, and on current of the thin film transistor is increased, and variation in electric characteristics is reduced. As a structure of semiconductor layers which form a channel formation region of a thin film transistor, a first semiconductor layer including a plurality of crystalline regions is provided on a gate insulating layer side; a second semiconductor layer having an amorphous structure is provided on a source region and drain region side; an insulating layer with a thickness small enough to allow carrier travel is provided between the first semiconductor layer and the second semiconductor layer. The first semiconductor layer is in contact with the gate insulating layer. The second semiconductor layer is provided on an opposite side to a face of the first semiconductor layer which is in contact with the gate insulating layer.

Claims (27)

1. A thin film transistor comprising:

a gate electrode over a substrate having an insulating surface;

a gate insulating layer over the gate electrode;

a first semiconductor layer comprising a plurality of crystalline regions on and in contact with the gate insulating film;

an insulating film covering the first semiconductor layer;

a second semiconductor layer comprising an amorphous structure on the insulating film; and

impurity semiconductor layers of one conductivity type, the impurity semiconductor layers forming a source region and a drain region.

2. The thin film transistor according to claim 1 , wherein in a region which does not reach the impurity semiconductor layers of one conductivity type, the first semiconductor layer includes an inverted conical or inverted pyramidal crystal having grown from a position apart from an interface between the gate insulating layer and the first semiconductor layer in a direction in which the first semiconductor layer is deposited.

3. The thin film transistor according to claim 1 , wherein an oxygen concentration and a nitrogen concentration in the first semiconductor layer which are measured by secondary ion mass spectrometry are 5×10 18 /cm 3 or less, and 1×10 20 /cm 3 to 1×10 21 /cm 3 inclusive, respectively.

4. The thin film transistor according to claim 3 , wherein a peak of the nitrogen concentration which is measured by secondary ion mass spectrometry is 3×10 20 /cm 3 to 1×10 21 /cm 3 inclusive at the interface between the gate insulating layer and the first semiconductor layer or a portion near the interface, and the nitrogen concentration decreases from the interface or the portion near the interface in a thickness direction of the first semiconductor layer.

5. The thin film transistor according to claim 2 , wherein in the first semiconductor layer, a point from which the inverted conical or inverted pyramidal crystal starts to grow is located in a region in which the nitrogen concentration measured by secondary ion mass spectrometry is higher than or equal to 1×10 20 /cm 3 and less than 3×10 20 /cm 3 .

6. The thin film transistor according to claim 1 , wherein the crystalline regions comprise single crystals.

7. The thin film transistor according to claim 6 , wherein the single crystals comprise twin crystals.

8. A thin film transistor comprising:

a gate electrode over a substrate having an insulating surface;

a gate insulating layer over the gate electrode;

a first semiconductor layer comprising a plurality of crystalline regions on and in contact with the gate insulating film;

an insulating film covering the first semiconductor layer;

a second semiconductor layer comprising an amorphous structure on the insulating film; and

impurity semiconductor layers of one conductivity type, the impurity semiconductor layers forming a source region and a drain region,

wherein the insulating layer is a monatomic layer.

9. The thin film transistor according to claim 8 , wherein in a region which does not reach the impurity semiconductor layers of one conductivity type, the first semiconductor layer includes an inverted conical or inverted pyramidal crystal having grown from a position apart from an interface between the gate insulating layer and the first semiconductor layer in a direction in which the first semiconductor layer is deposited.

10. The thin film transistor according to claim 8 , wherein an oxygen concentration and a nitrogen concentration in the first semiconductor layer which are measured by secondary ion mass spectrometry are 5×10 18 /cm 3 or less, and 1×10 20 /cm 3 to 1×10 21 /cm 3 inclusive, respectively.

11. The thin film transistor according to claim 10 , wherein a peak of the nitrogen concentration which is measured by secondary ion mass spectrometry is 3×10 20 /cm 3 to 1×10 21 /cm 3 inclusive at the interface between the gate insulating layer and the first semiconductor layer or a portion near the interface, and the nitrogen concentration decreases from the interface or the portion near the interface in a thickness direction of the first semiconductor layer.

12. The thin film transistor according to claim 9 , wherein in the first semiconductor layer, a point from which the inverted conical or inverted pyramidal crystal starts to grow is located in a region in which the nitrogen concentration measured by secondary ion mass spectrometry is higher than or equal to 1×10 20 /cm 3 and less than 3×10 20 /cm 3 .

13. The thin film transistor according to claim 8 , wherein the crystalline regions comprise single crystals.

14. The thin film transistor according to claim 13 , wherein the single crystals comprise twin crystals.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2009
From: YAMAZAKI, SHUNPEI; EGI, YUJI; SASAGAWA, SHINYA; KURATA, MOTOMU
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 022769/0518 →
Priority Claims (1)
JP 2008-109629 · Apr 18, 2008 · national
Continuity (1)
Related Publication 20100096637A1 · Apr 22, 2010