Modeling full and half cycle clock variability
View Patent ↗A modeling system includes a processor with software that performs static timing analysis (STA) on a design model. STA software executes a static timing analysis (STA) run with shortened clock cycles to model full cycle clock variability. Designers or other entities interpret the results of the shortened STA run data by performing modeling on the output data to generate slack data for design model data paths. STA software executes an STA run with an extended clock cycle to automatically separate half cycle data path (HCDP) slack data from full cycle data path (FCDP) slack data. The full and half cycle clock variability method may automatically adjust slack data for all half cycle data paths (HCDP)s to account for the additional half cycle variation (AHCV) and half cycle clock edge variability that may penalize the design model results in a real hardware implementation.
1. A method of modeling half cycle clock variation:
performing, by a static timing analyzer, a first static timing analysis (STA-1) on a design model that includes a launch storage element (LSE) and a capture storage element (CSE) with combinational logic therebetween, the design model including full cycle data paths and half cycle data paths, a main clock signal being applied to the launch storage element (LSE) and the capture storage element (CSE), wherein the first static timing analysis (STA-1) is performed using a shortened clock period to model full clock cycle variability (FCV) to provide slack information including worst case slack information (WS) and half clock cycle variability information (HCV);
determining, by the static timing analyzer, a clock period extension (CPE) value from the worst case slack (WS) information and the half clock cycle variability (HCV) information;
performing, by the static timing analyzer, a second static timing analysis (STA-2) using the clock period extension (CPE) value applied to the main clock signal to generate an extended clock signal and corresponding second static timing analysis (STA-2) slack information; and
identifying, by the static timing analyzer, failing half cycle data paths from the second static timing analysis (STA-2) slack information.
2. The method of claim 1 , further comprising:
normalizing, by the static timing analyzer, the second static timing analysis (STA-2) slack information corresponding to the identified half cycle data paths to provide normalized second static timing analysis (STA-2) slack data values.
3. The method of claim 2 , further comprising selecting, by the static timing analyzer, from the normalized second static timing analysis (STA-2) slack data values those slack data values that are negative to identify the failing half cycle data paths.
4. The method of claim 2 , further comprising separating the failing half cycle data paths from a failing full cycle data path by using second static timing analysis (STA-2) slack data values.
5. The method of claim 2 , wherein launch storage element initiates a full cycle data path on a leading edge of the main clock signal and end on a next leading edge of the main clock signal.
6. The method of claim 2 , wherein launch storage elements initiate a half cycle data path on a leading edge of the main clock signal and end on a next trailing edge of the main clock signal.
7. The method of claim 1 , wherein the launch storage element is a transparent storage element and the capture storage element is a transparent storage element.
8. A modeling system comprising:
a processor;
a memory store, coupled to the processor, configured to:
perform a first static timing analysis (STA-1) on a design model that includes a launch storage element (LSE) and a capture storage element (CSE) with combinational logic therebetween, the design model including full cycle data paths and half cycle data paths, a main clock signal being applied to the launch storage element (LSE) and the capture storage element (CSE), wherein the first static timing analysis (STA-1) is performed using a shortened clock period to model full clock cycle variability (FCV) to provide slack information including worst case slack information (WS) and half clock cycle variability information (HCV);
determine a clock period extension (CPE) value from the worst case slack (WS) information and the half clock cycle variability (HCV) information;
perform a second static timing analysis (STA-2) using the clock period extension (CPE) value applied to the main clock signal to generate an extended clock signal and corresponding second static timing analysis (STA-2) slack information; and
identify failing half cycle data paths from the second static timing analysis (STA-2) slack information.
9. The system of claim 8 , wherein the memory store is further configured to normalize the second static timing analysis (STA-2) slack information corresponding to the identified half cycle data paths to provide normalized second static timing analysis (STA-2) slack data values.
10. The system of claim 9 , wherein the memory store is further configured to select from the normalized second static timing analysis (STA-2) slack data values those slack data values that are negative to identify the failing half cycle data paths.
11. The system of claim 9 , wherein the memory store is further configured to separate the failing half cycle data paths from a failing full cycle data path by using second static timing analysis (STA-2) slack data values.
12. The system of claim 9 , wherein the memory store is configured to cause the launch storage element to initiate a full cycle data path on a leading edge of the main clock signal and end on a next leading edge of the main clock signal.
13. The system of claim 9 , wherein the memory store is configured to cause the launch storage element to initiate a half cycle data path on a leading edge of the main clock signal and end on a next trailing edge of the main clock signal.
14. The system of claim 8 , wherein the launch storage element comprises a first transparent storage element and the capture storage element comprises a second transparent storage element.
15. A computer program product comprising:
a non-transitory computer readable storage medium;
first instructions that perform a first static timing analysis (STA-1) on a design model that includes a launch storage element (LSE) and a capture storage element (CSE) with combinational logic therebetween, the design model including full cycle data paths and half cycle data paths, a main clock signal being applied to the launch storage element (LSE) and the capture storage element (CSE), wherein the first static timing analysis (STA-1) is performed using a shortened clock period to model full clock cycle variability (FCV) to provide slack information including worst case slack information (WS) and half clock cycle variability information (HCV);
second instructions that determine a clock period extension (CPE) value from the worst case slack (WS) information and the half clock cycle variability (HCV) information;
third instructions that perform a second static timing analysis (STA-2) using the clock period extension (CPE) value applied to the main clock signal to generate an extended clock signal and corresponding second static timing analysis (STA-2) slack information; and
fourth instructions that identify failing half cycle data paths from the second static timing analysis (STA-2) slack information;
wherein the first, second, third and fourth program instructions are stored on the non-transitory computer readable storage medium.
16. The computer program product of claim 15 , further comprising instructions that normalize the second static timing analysis (STA-2) slack information corresponding to the identified half cycle data paths to provide normalized second static timing analysis (STA-2) slack data values.
17. The computer program product of claim 16 , further comprising instructions that select from the normalized second static timing analysis (STA-2) slack data values those slack data values that are negative to identify the failing half cycle data paths.
18. The computer program product of claim 16 , further comprising instructions that separate the failing half cycle data paths from a failing full cycle data path by using second static timing analysis (STA-2) slack data values.
19. The computer program product of claim 16 , further comprising instructions that cause the launch storage element to initiate a full cycle data path on a leading edge of the main clock signal and end on a next leading edge of the main clock signal.
20. The computer program product of claim 16 , further comprising instructions that cause the launch storage element to initiate a half cycle data path on a leading edge of the main clock signal and end on a next trailing edge of the main clock signal.