Thin film transistor, method of manufacturing the same and flat panel display device having the same
A thin film transistor (TFT) using an oxide semiconductor as an active layer, a method of manufacturing the TFT, and a flat panel display device having the TFT include source and drain electrodes formed on a substrate; an active layer formed of an oxide semiconductor disposed on the source and drain electrodes; a gate electrode; and an interfacial stability layer formed on at least one of top and bottom surfaces of the active layer. In the TFT, the interfacial stability layer is formed of an oxide having a band gap of 3.0 to 8.0 eV. Since the interfacial stability layer has the same characteristics as a gate insulating layer and a passivation layer, chemically high interface stability is maintained. Since the interfacial stability layer has a band gap equal to or greater than that of the active layer, charge trapping is physically prevented.
1. A thin film transistor (TFT), comprising:
a substrate;
source and drain electrodes formed on the substrate;
an active layer formed of an oxide semiconductor and formed to at least partially overlap both of the source and drain electrodes;
a gate insulating layer formed on the substrate to cover the active layer and the source and drain electrodes;
a gate electrode formed on the gate insulating layer and insulated from the active layer by the gate insulating layer; and
an interfacial stability layer formed on at least one of top and bottom surfaces of the active layer, the interfacial stability layer being formed of an oxide having a band gap of 3.0 to 8.0 eV,
wherein a portion of the interfacial stability layer is interposed between the source and drain electrodes and the active layer.
2. The thin film transistor of claim 1 , wherein the oxide semiconductor comprises zinc oxide (ZnO).
3. The thin film transistor of claim 2 , wherein the oxide semiconductor is doped with at least one ion of gallium (Ga), indium (In), tin (Sn), zirconium (Zr), hafnium (Hf), cadmium (Cd), silver (Ag), copper (Cu), germanium (Ge), gadolinium (Gd) and vanadium (V).
4. The thin film transistor of claim 1 , wherein the interfacial stability layer comprises one selected from the group consisting of SiO x , SiO x N y , SiO x C y , SiO x C y H z , SiO x F y , GeO x , GdO x , AlO x , GaO x , SbO, ZrO, HfO, TaO, YO x , VO x , MgO x , CaO x , BaO x , SrO x , and spin on glass (SOG).
5. The thin film transistor of claim 1 , wherein the oxygen concentration of the interfacial stability layer is 10 +19 /cm 3 or lower.
6. The thin film transistor of claim 1 , wherein the interfacial stability layer is formed wider than the active layer when the interfacial stability layer is formed at the bottom surface of the active layer.
7. A thin film transistor (TFT), comprising:
a substrate;
source and drain electrodes formed on the substrate;
an active layer formed of an oxide semiconductor and formed to at least partially overlap both of the source and drain electrodes;
a gate insulating layer formed on the substrate to cover the active layer and the source and drain electrodes;
a gate electrode formed on the gate insulating layer and insulated from the active layer by the gate insulating layer; and
an interfacial stability layer formed on at least one of top and bottom surfaces of the active layer, the interfacial stability layer being formed of an oxide having a band gap equal to or greater than a band gap of the active layer,
wherein a portion of the interfacial stability layer is interposed between the source and drain electrodes and the active layer.
8. A thin film transistor (TFT), comprising:
a substrate;
source and drain electrodes formed on the substrate;
an active layer formed of an oxide semiconductor and formed to at least partially overlap both of the source and drain electrodes;
a gate insulating layer formed on the substrate to cover the active layer and the source and drain electrodes;
a gate electrode formed on the gate insulating layer and insulated from the active layer by the gate insulating layer; and
an interfacial stability layer formed on at least one of top and bottom surfaces of the active layer, an oxygen concentration of the interfacial stability layer being 10 19 /cm 3 or lower,
wherein a portion of the interfacial stability layer is interposed between the source and drain electrodes and the active layer.