Semiconductor device and method of fabrication
View Patent ↗A semiconductor device includes a first die pad, a first semiconductor chip provided on the first die pad, a second die pad, a second semiconductor chip provided on the second die pad, and a sealing resin made of a first resin material, sealing the first die pad, the first semiconductor chip, the second die pad and the second semiconductor chip. A lower surface of the first semiconductor chip is connected to the first die pad. A first portion of a lower surface of the second semiconductor chip is connected to the second die pad, and a second portion not connected to the second die pad of the lower surface of the second semiconductor chip is connected to an upper surface of the first semiconductor chip via a second resin material different from the first resin material.
1. A semiconductor device comprising:
a first die pad;
a first semiconductor chip provided on the first die pad;
a second die pad;
a second semiconductor chip provided on the second die pad; and
a sealing resin made of a first resin material, sealing the first die pad, the first semiconductor chip, the second die pad and the second semiconductor chip,
wherein a lower surface of the first semiconductor chip is connected to the first die pad, and
a first portion of a lower surface of the second semiconductor chip is connected to the second die pad, and a second portion not connected to the second die pad of the lower surface of the second semiconductor chip is connected to an upper surface of the first semiconductor chip via a second resin material different from the first resin material.
2. The semiconductor device of claim 1 , wherein
the first and second die pads are electrically isolated from each other, and
the first and second die pads are provided at positions different from each other in a vertical direction.
3. The semiconductor device of claim 1 , wherein
one of the first and second die pads is grounded.
4. The semiconductor device of claim 1 , wherein
a thermal conductivity of the second resin material is lower than a thermal conductivity of the first resin material.
5. The semiconductor device of claim 1 , wherein
the lower surface of the first die pad is exposed from the sealing resin.
6. The semiconductor device of claim 1 , wherein
the first semiconductor chip has a high heat generation circuit region having a relatively high amount of heat generated during a circuit operation and a low heat generation circuit region having a relatively low amount of heat generated during the circuit operation, and
there is space between a region contacting the second resin material of the first semiconductor chip, and the high heat generation circuit region.
7. The semiconductor device of claim 6 , wherein
a length of the space is larger than or equal to a thickness of the first semiconductor chip.