Method and structure for solving the evil-twin problem
A register file, in a processor, includes a first plurality of registers of a first size, n-bits. A decoder uses a mapping that divides the register file into a second plurality M of registers having a second size. Each of the registers having the second size is assigned a different name in a continuous name space. Each register of the second size includes a plurality N of registers of the first size, n-bits. Each register in the plurality N of registers is assigned the same name as the register of the second size that includes that plurality. State information is maintained in the register file for each n-bit register. The dependence of an instruction on other instructions is detected through the continuous name space. The state information allows the processor to determine when the information in any portion, or all, of a register is valid.
1. A processor comprising:
a continuous name space mapped register file comprising a plurality of registers, wherein each register in the plurality of registers is of a first size, wherein each register is associated with one of a low portion or a high portion of a register of a second size, and wherein each low portion and each high portion has a valid bit associated with that portion;
a decode unit for decoding
first instructions having sources and destinations of the first size, and
second instructions having sources and destinations of the second size,
wherein the second size is an even integer multiple n of the first size; and
a mapping unit for mapping register names for the first instructions, and register names for the second instructions, into a common name space, by
(i) for instructions having sources and destinations of the first size and a register of the first size in a named set of registers in the plurality of registers, asserting the valid bit for one of the low portion or the high portion of that named set of registers, and mapping the instruction accordingly, and
(ii) for instructions having sources and destinations of the second size and a register of the second size in the named set of registers, asserting the valid bits for both the low and high portions of that named set of registers, and mapping the instruction accordingly.
2. The processor of claim 1 wherein each register of the first size has a corresponding valid bit.
3. The processor of claim 1 further comprising:
a scoreboard having an entry for each register of the first size.
4. The processor of claim 1 further comprising:
an execution pipe coupled to the register file, wherein upon the execution pipe writing a result to only one register in a set of n registers, a valid bit is asserted only for the one register.
5. The processor of claim 1 further comprising:
an execution pipe coupled to the register file, wherein upon the execution pipe writing a result to all registers in a set of n registers, a valid bit for each of the n registers is asserted.
6. The processor of claim 4 further wherein upon the execution pipe writing a result to all registers in the set of n registers, a valid bit for each of the n registers is asserted.
7. The processor of claim 1 wherein n is two and the first size is thirty-two bits.
8. The processor of claim 1 further comprising:
a content addressable memory with only a shared port, wherein said register file is included in said content addressable memory.
9. The processor of claim 1 wherein the register file is a working register file.
10. A method for solving an evil twin problem in a processor supporting first instructions with sources and destinations of a first size, and second instructions having sources and destinations of a second size, where the second size is an even integer multiple n of the first size, the method comprising:
providing a continuous name space mapped register file comprising a plurality of registers, wherein each register in the plurality of registers is of a first size, wherein each register is associated with one of a low portion or a high portion of a register of the second size, and wherein each low portion and each high portion has a valid bit associated with that portion;
decoding, by a decoding pipe of the processor, the first instructions having sources and destinations of the first size, and the second instructions having sources and destinations of the second size, wherein the decoding further comprises
mapping register names for the first instructions and register names for the second instructions into a common name space by
(i) for instructions having sources and destinations of the first size and a register of the first size in a named set of registers in the plurality of registers, asserting the valid bit for one of the low portion or the high portion of that named set of registers, and mapping the instruction accordingly, and
(ii) for instructions having sources and destinations of the second size and a register of the second size in the named set of registers, asserting the valid bits for both the low and high portions of that named set of registers, and mapping the instruction accordingly.
11. The method of claim 10 further comprising:
maintaining separate state information for each register of the first size in the register file.
12. The method of claim 10 further comprising:
maintaining an entry for each of the registers of the first size in a scoreboard.
13. The method of claim 10 further comprising:
asserting only a valid bit for one register in a set of n registers upon an execution pipe in the processor writing a result to only the one register in the set of n registers.
14. The method of claim 10 further comprising:
asserting a valid bit for each register in a set of n registers upon an execution pipe writing a result to all registers in the set of n registers.
15. The method of claim 13 further comprising:
asserting a valid bit for each register in the set of n registers upon the execution pipe writing a result to all registers in the set of n registers.
16. The method of claim 10 wherein n is two and the first size is thirty-two bits.
17. The method of claim 10 wherein the register file is included in a content addressable memory with only a shared port.
18. The method of claim 10 wherein the register file is a working register file.
19. A system comprising:
a memory; and
a processor, coupled to the memory, comprising:
a continuous name space mapped register file comprising a plurality of registers wherein each register in the plurality of registers is of a first size, wherein each register is associated with one of a low portion or a high portion of a register of a second size, and wherein each low portion and each high portion has a valid bit associated with that portion;
a decode unit for decoding
first instructions having sources and destinations of the first size, and
second instructions having sources and destinations of the second size,
wherein the second size is an even integer multiple n of the first size; and
a mapping unit for mapping register names for the first instructions, and register names for the second instructions, into a common name space, by
(i) for instructions having sources and destinations of the first size and ach a register of the first size in a named set of registers in the plurality of registers, asserting the valid bit for one of the low portion or the high portion of that named set of registers, and mapping the instruction accordingly, and
(ii) for instructions having sources and destinations of the second size and a register of the second size in the named set of registers, asserting the valid bits for both the low and high portions of that named set of registers, and mapping the instruction accordingly.
20. The system of claim 19 further wherein the processor further comprises:
an execution pipe coupled to the register file,
wherein upon the execution pipe writing a result to only one register in a set of n registers, a valid bit is asserted for only the one register; and
upon the execution pipe writing a result to all registers in the set of n registers, a valid bit for each of the n registers is asserted.