Thread-to-core mapping based on thread deadline, thread demand, and hardware characteristics data collected by a performance counter

1. A computing system, comprising:

a multi-core processor comprising a plurality of processor cores on a chip;

a performance counter circuit configured to collect data relating to execution characteristics of a particular thread to determine hardware capabilities of the processor cores, the performance counter circuit including a register built into the chip to store counts of hardware related activities of the processor cores; and

a core controller configured to map the particular thread to the plurality of processor cores based in part on the determined hardware capabilities of the processor cores,

wherein the processor cores are heterogeneous cores having differing processing capabilities, including at least one heterogeneous core having a streaming single instruction, multiple data (SIMD) extensions (SSE) accelerator that is different from an accelerator of another one of the heterogeneous cores,

wherein when the particular thread includes an SSE demand, which is a larger SSE demand relative to other threads, the core controller is configured to map the particular thread to the at least one heterogeneous core having the SSE accelerator,

wherein prior to a migration of the particular thread from a first core of the plurality of processor cores to a second core of the plurality of processor cores, the core controller is configured to pre-fetch cache data from a first cache associated with the first core of the plurality of processor cores, and the core controller is further configured to transfer the pre-fetched cache data to a second cache associated with the second core of the plurality of processor cores, wherein the pre-fetched cache data includes at least hits or evictions, associated with the particular thread; and

wherein the core controller is further configured to determine that the particular thread is falling behind a target deadline, the determination that the particular thread is falling behind the target deadline is based on the data collected by the performance counter circuit, and the core controller is configured to map the particular thread to one of the processor cores based on the determination that the particular thread is falling behind the target deadline.

2. The computing system of claim 1 , wherein the performance counter circuit is configured to collect thread execution data from one of the plurality of processor cores.

3. The computing system of claim 1 , wherein the performance counter circuit is configured to collect cache line eviction data from a cache associated with one of the plurality of processor cores.

4. The computing system of claim 1 , wherein the performance counter circuit is configured to collect real time computing data from a processor core.

5. A method to operate a multi-core computing system including a plurality of processor cores on a chip, the method comprising:

executing a software application program resulting in an execution of a particular thread;

collecting data relating to performance of the plurality of processor cores using a performance counter circuit, the performance counter circuit including a register built into the chip to store counts of hardware related activities of the processor cores;

determining hardware capabilities of the processor cores based on the data relating to the performance of the processor cores; and

mapping, via a core controller, the particular thread to one of the plurality of processor cores based in part on the determined hardware capabilities of the processor cores,

wherein the processor cores are heterogeneous cores having differing processing capabilities, including at least one heterogeneous core having a streaming single instruction, multiple data (SIMD) extensions (SSE) accelerator that is different from an accelerator of another one of the heterogeneous cores,

wherein when the particular thread includes an SSE demand, which is a larger SSE demand relative to other threads, the core controller is configured to map the particular thread to the at least one heterogeneous core having the SSE accelerator,

wherein prior to a migration of the particular thread from a first core of the plurality of processor cores to a second core of the plurality of processor cores, the core controller is configured to pre-fetch cache data from a first cache associated with the first core of the plurality of processor cores, and the core controller is further configured to transfer the pre-fetched cache data to a second cache associated with the second core of the plurality of processor cores, wherein the pre-fetched cache data includes at least hits or evictions, associated with the particular thread, and

wherein the core controller is further configured to determine that the particular thread is falling behind a target deadline, the determination that the particular thread is falling behind the target deadline is based on the data collected by the performance counter circuit, and the core controller is configured to map the particular thread to one of the processor cores based on the determination that the particular thread is falling behind the target deadline.

6. The method of claim 5 , wherein collecting data comprises collecting thread execution data associated with one of the plurality of processor cores.

7. The method of claim 5 , wherein mapping the particular thread comprises mapping the data collected by the performance counter circuit to one of the plurality of processor cores.

8. The method of claim 5 , wherein collecting computing data is done in real time.

9. The method of claim 5 , wherein collecting data comprises collecting cache line eviction data of a cache associated with one of the plurality of processor cores.

10. A non-transitory computer accessible medium having stored thereon computer executable instructions to perform a procedure to map threads to processor cores in a multi-core processor system, the procedure comprising:

collecting data relating to performance of the multi-core processor system using a performance counter circuit, the performance counter circuit including a register built into a chip to store counts of hardware-related activities of the processor cores;

determining hardware capabilities of the processor cores based on the data relating to the performance of the multi-core processor system; and

mapping, via a core controller, a particular thread to one of the processor cores based in part on the determined hardware capabilities of the processor cores,

wherein the processor cores are heterogeneous cores having differing processing capabilities, including at least one heterogeneous core having a streaming single instruction, multiple data (SIMD) extensions (SSE) accelerator that is different from an accelerator of another one of the heterogeneous cores,

wherein when the particular thread includes an SSE demand, which is a larger SSE demand relative to other threads, the core controller is configured to map the particular thread to the at least one heterogeneous core having the SSE accelerator,

wherein prior to a migration of the particular thread from a first core of the plurality of processor cores to a second core of the plurality of processor cores, the core controller is configured to pre-fetch cache data from a first cache associated with the first core of the plurality of processor cores, and the core controller is further configured to transfer the pre-fetched cache data to a second cache associated with the second core of the plurality of processor cores, wherein the pre-fetched cache data includes at least hits or evictions, associated with the particular thread, and

wherein the core controller is further configured to determine that the particular thread is falling behind a target deadline, the determination that the particular thread is falling behind the target deadline is based on the data collected by the performance counter circuit, and the core controller is configured to map the particular thread to one of the processor cores based on the determination that the particular thread is falling behind the target deadline.

11. The computer accessible medium of claim 10 , wherein collecting data comprises collecting thread execution data associated with one or more of the processor cores.