Patent Assignment
Reel/Frame 053378/0053
Assignment of Assignor's Interest
Recorded: 2020-08-03
Pages: 10
Assignor
EMPIRE TECHNOLOGY DEVELOPMENT, LLC
Executed: 2020-07-06
Assignee
MERCURY KINGDOM ASSETS LIMITED
C/O TRIDENT TRUST COMPANY (B.V.I.) LIMITED, TRIDENT CHAMBERS, P.O. BOX 146, ROAD TOWN,, TORTOLA, VIRGIN ISLANDS, BRITISH
Covered Properties
(35)
Multiprocessor Cache Prefetch with Off-Chip Bandwidth Allocation
Interrupt Arbitration for Multiprocessors
Thread-To-Core Mapping Based on Thread Deadline, Thread Demand, and Hardware Characteristics Data Collected by a Performance Counter
Compiler Based Cache Allocation
Dynamic Scheduling Interrupt Controller for Multiprocessors
Interrupt Optimization for Multiprocessors
Allocating Processor Cores with Cache Memory Associativity
Allocating Threads to Cores Based on Threads Falling Behind Thread Completion Target Deadline
Mapping Thread Phases Onto Heterogeneous Cores Based on Execution Characteristics and Cache Line Eviction Counts
Interrupt Masking for Multi-Core Processors
Processor Core Clock Rate Selection
Domain Based Cache Coherence Protocol
Directory-Based Coherence Caching
Data Storage and Access in Multi-Core Processor Architectures
Accelerating Cache State Transfer on a Directory-Based Multicore Architecture
Data Storage and Access in Multi-Core Processor Architectures
Sectored Cache with a Tag Structure Capable of Tracking Sectors of Data Stored for a Particular Cache Way
Cache Based Key-Value Store Mapping and Replication
Resource Allocation in Multi-Core Architectures
Energy Conservation in a Multicore Chip
Virtual Cache Directory in Multi-Processor Architectures
Cache Coherence Directory in Multi-Processor Architectures
Dynamically Managing Distribution of Data and Computation Across Cores for Sequential Programs
Aggregating Cache Eviction Notifications to a Directory
Management of Chip Multiprocessor Cooperative Caching Based on Eviction Rate
Hybrid Routers in Multicore Architectures
Processor Core Clock Rate Selection
Locating Cached Data in a Multi-Core Processor
Sequential Access of Cache Data
Resource Allocation in Multi-Core Architectures
Cache Lookup Bypass in Multi-Level Cache Systems
Thread and Data Assignment in Multi-Core Processors Based on Cache Miss Data
Accelerating Cache State Transfer on a Directory-Based Multicore Architecture
Management of Chip Multiprocessor Cooperative Caching Based on Eviction Rate
Thread and Data Assignment in Multi-Core Processors Based on Cache Miss Data and Thread Category
Related Assignments
(2)
Other recorded transfers of the patents in this record — the chain of ownership.