Allocating processor cores with cache memory associativity

1. A computing system, comprising:

a multi-core processor comprising a plurality of individual processor cores;

a cache memory that is configured to be accessible to at least some of the plurality of the individual processor cores; and

a cache controller coupled to the multi-core processor, the cache controller configured to allocate a memory space within the cache memory, the cache controller further being configured to facilitate access to the cache memory by at least some of the plurality of the individual processor cores with respective levels of associativity that are different for at least some of the plurality of the individual processor cores.

2. The computing system of claim 1 , further comprising a core controller coupled to the plurality of individual processor cores, the core controller being configured to determine which processing tasks are to be processed by each of the plurality of individual processor cores.

3. The computing system of claim 1 , further comprising a core controller coupled to the plurality of individual processor cores, the core controller being configured to determine which threads are to be stored in the cache memory.

4. The computing system of claim 1 wherein at least some of the individual processor cores comprise respective branch predictors configured to identify strided references, and wherein the computing system further comprises a core controller coupled to at least some of the plurality of individual processor cores that are configured to access the cache memory, the core controller being configured to allocate memory space within the cache memory based at least in part on the identification of the strided references.

5. The computing system of claim 1 wherein the computing system further comprises a core controller coupled to the plurality of individual processor cores, the core controller being configured to allocate memory space within the cache memory to the individual processor cores based at least in part on hardware characteristics associated with each of the individual processor cores.

6. The computing system of claim 1 wherein the cache controller is configured to assign to each of the individual processor cores that can access the cache memory a respective level of associativity for each of the rows of the cache memory.

7. The computing system of claim 1 wherein each of the individual processor cores that is configured to access the cache memory is configured to output an address comprising a plurality of middle order address bits, and wherein the cache controller is configured to use the middle order address bits as an index to select a respective row of memory cells in the cache memory.

8. The computing system of claim 1 wherein each of the individual processor cores that is configured to access the cache memory is configured to output an address comprising a plurality of high order address bits, and wherein the cache controller is configured to use the high order address bits as respective tags that are stored in the cache memory by comparing the high order address bits of an address from one of the individual processor cores to each of the stored tags, the cache controller being configured to be responsive to a match between the high order address bits of an address and one of the stored tags to cause the one of the individual processor cores individual processor core to access data stored at a location in the cache memory corresponding to the location at which the tag is stored.

9. The computing system of claim 1 wherein each of the individual processor cores that is configured to access the cache memory is configured to output an address comprising a plurality of low order address bits, and wherein the cache controller is configured to use the low order address bits to select a plurality of bits of data stored in the row of the cache memory.

10. The computing system of claim 1 wherein each column of the cache memory is configured to store a bit vector, and wherein the cache controller is configured to use the bit vector to determine which of the individual processor cores may access the respective column of the cache memory.

11. The computing system of claim 1 wherein the cache controller is configured to cause instructions and data to be written to the cache memory using a write-back cache write policy.

12. The computing system of claim 1 wherein the cache controller is configured to allow the cache memory to be accessed by each of the individual processor cores that is configured to access the cache memory with a respective level of associativity based at least in part on hardware characteristics associated with each of the individual processor cores.

13. The computing system of claim 1 wherein the cache controller is configured to allow the cache memory to be accessed by at least some of the plurality of individual processor cores with a respective level of associativity based at least in part on an execution characteristic of threads of execution associated with the at least some of the plurality of individual processor cores.

14. A method for allowing a plurality of processor cores to access a cache memory, the method comprising:

assigning a respective level of cache memory associativity to each of the plurality of processor cores, the level of cache memory associativity assigned to at least one of the plurality of processor cores being different from the level of cache memory associativity assigned to a least another one of the plurality of processor cores; and

facilitating each of the plurality of processor cores to access the cache memory with the respective assigned level of associativity.

15. The method of claim 14 , further comprising evicting data stored in the cache memory using a least recently used replacement policy.

16. The method of claim 14 wherein assigning a respective level of associativity to each of the plurality of processor cores comprises assigning to each of the plurality of processor cores that can access the cache memory a respective level of associativity for each of the rows of cache memory, the level of associativity assigned to some of the rows being different from the level of associativity assigned to other of the rows.

17. The method of claim 14 , further comprising:

identifying threads that contain more than a specific quantity of non-looped instructions;

marking the identified threads with a non-cacheable flag; and

inhibiting the marked threads from being stored in the cache memory.

18. The method of claim 14 wherein assigning a respective level of associativity to each of the plurality of processor cores comprises dynamically assigning a level of associativity to each of the plurality of processor cores such that the assigned level of associatively varies with time.

19. A non-transitory computer accessible medium having stored thereon computer executable instructions for performing a procedure for allowing a plurality of processor cores to access a cache memory in a computing system, the procedure comprising:

assigning a respective level of cache memory associativity to each of the plurality of processor cores, the level of cache memory associativity assigned to at least one of the plurality of processor cores being different from the level of cache memory associativity assigned to a least another one of the plurality of processor cores; and

allowing each of the plurality of processor cores to access the cache memory with the respective assigned level of associativity.

20. The computer accessible medium of claim 19 , wherein assigning a respective level of cache memory associativity to each of the plurality of processor cores comprises associating each of the plurality of processor cores with specific columns in each of a plurality of rows of the cache memory.