Idle mode power consumption reduction in wireless communications
View Patent ↗Idle mode power consumption reduction in wireless communications. Within a wireless communication device that is operative to communicate with any one of a number of servicing cells, paging broadcasts from more than one of these servicing cells are received and undergo only a limited amount of processing before being stored for use in subsequent processing that may be performed later. This partitioned processing allows the turning off of certain components that are not needed and/or no longer needed for determining the system frame numbers associated with various servicing cells to effectuate timing synchronization. Certain modules within such a wireless communication device may perform processing using the full capabilities of the wireless communication device to generate initially processed signal, and then after such signals are stored, then only partial processing capability of the wireless communication device may be employed, even though perhaps being slower, to complete the processing.
1. An apparatus, comprising:
a radio frequency (RF) module to perform parallel processing of a plurality of paging broadcasts corresponding to a plurality of servicing cells to generate a plurality of demodulated signals;
a hardware accelerator module, coupled to the RF module, to process the plurality of demodulated signals to generate a corresponding plurality of soft symbol groups such that each soft symbol group corresponds to one of the plurality of servicing cells, wherein the hardware accelerator module includes a memory module to store each of the plurality of soft symbol groups;
a host processor module, coupled to the hardware accelerator module, to:
perform serial Viterbi decoding of each of the plurality of soft symbol groups to generate a plurality of broadcast channel transport blocks such that each broadcast channel transport block corresponds to one of the plurality of servicing cells; and
perform serial processing of the plurality of broadcast channel transport blocks to generate a plurality of system frame numbers, for use in timing synchronization with respect to the plurality of servicing cells, such that each frame number corresponds to one of the plurality of servicing cells; and
a control module, coupled to the RF module, the hardware accelerator module, and the host processor module, to:
turn on each of the RF module, the hardware accelerator module, and the host processor module at a beginning of a wakeup period;
turn off the RF module after each of the plurality of soft symbol groups is stored in the memory module;
turn off the hardware accelerator module after the host processor module has generated the plurality of broadcast channel transport blocks; and
turn off the memory module and the host processor module after the plurality of system frame numbers is generated and output to a higher protocol layer module.
2. The apparatus of claim 1 , wherein:
the plurality of paging broadcasts received via a Paging Indicator Channel (PICH).
3. The apparatus of claim 1 , wherein:
the hardware accelerator module further includes at least one of a descrambler, a despreader, a pilot filtering module, a rake combining module, and a deinterleaver module, to process the plurality of demodulated signals to generate the corresponding plurality of soft symbol groups.
4. The apparatus of claim 1 , wherein:
the hardware accelerator module further includes a deinterleaver module and at least one other module;
the at least one other module to perform parallel processing of the plurality of demodulated signals to generate a processed plurality of demodulated signals; and
the deinterleaver module to perform serial processing of the processed plurality of demodulated signals to generate the corresponding plurality of soft symbol groups.
5. The apparatus of claim 4 , wherein:
the memory module to store each of the processed plurality of demodulated signals; and
the deinterleaver module to retrieve serially the processed plurality of demodulated signals from the memory module in accordance with performing serial processing of the processed plurality of demodulated signals to generate the corresponding plurality of soft symbol groups.
6. The apparatus of claim 1 , wherein:
the hardware accelerator module further includes a deinterleaver module that deinterleaves each of the plurality of soft symbol groups before outputting them to the host processor module.
7. The apparatus of claim 1 , wherein:
the hardware accelerator module includes a plurality of rake fingers; and
each of the plurality of rake fingers to process a respective one of the plurality of demodulated signals to generate a respective one of the corresponding plurality of soft symbol groups.
8. The apparatus of claim 7 , wherein:
each of the plurality of rake fingers includes a respective at least one of a descrambler, a despreader, and a pilot filtering module to process the respective one of the plurality of demodulated signals to generate the respective one of the corresponding plurality of soft symbol groups.
9. The apparatus of claim 1 , wherein:
the apparatus is operative within a wideband code division multiple access (WCDMA) communication system; and
each of the plurality of servicing cells operates in accordance with WCDMA.
10. The apparatus of claim 1 , wherein:
the apparatus is a wireless communication device; and
the wireless communication device is a laptop host computer, a personal digital assistant host, a personal computer host, or a cellular telephone host.
11. An apparatus, comprising:
a radio frequency (RF) module to perform parallel processing of a plurality of paging broadcasts corresponding to a plurality of servicing cells to generate a plurality of demodulated signals;
a baseband processing module, coupled to the RF module, to perform parallel processing of the plurality of demodulated signals to generate a corresponding plurality of soft symbol groups such that each soft symbol group corresponds to one of the plurality of servicing cells;
a memory module, coupled to the baseband processing module, to store each of the plurality of soft symbol groups;
a deinterleaver module, coupled to the memory module, to perform serial processing of each soft symbol group to generate a corresponding plurality of deinterleaved soft symbol groups;
a host processor module, coupled to the deinterleaver module, to:
perform serial Viterbi decoding of each of the plurality of deinterleaved soft symbol groups to generate a plurality of broadcast channel transport blocks such that each broadcast channel transport block corresponds to one of the plurality of servicing cells; and
perform serial processing of the plurality of broadcast channel transport blocks to generate a plurality of system frame numbers, for use in timing synchronization with respect to the plurality of servicing cells, such that each frame number corresponds to one of the plurality of servicing cells; and
a control module, coupled to the RF module, the baseband processing module, the memory module, the deinterleaver module, and the host processor module, to:
turn on each of the RF module, the baseband processing module, the memory module, the deinterleaver module, and the host processor module at a beginning of a wakeup period;
turn off the RF module and the baseband processing module after each of the plurality of soft symbol groups is stored in the memory module;
turn off the memory module and the deinterleaver module after the host processor module has generated the plurality of broadcast channel transport blocks; and
turn off the host processor module after the plurality of system frame numbers is generated and output to a higher protocol layer module.
12. The apparatus of claim 11 , wherein:
the plurality of paging broadcasts received via a Paging Indicator Channel (PICH).
13. The apparatus of claim 11 , wherein:
the RF module includes a plurality of rake fingers; and
each of the plurality of rake fingers to process a respective one of the plurality of paging broadcasts to generate a respective one of the corresponding plurality of demodulated signals.
14. The apparatus of claim 11 , wherein:
the baseband processing module includes a plurality of rake fingers; and
each of the plurality of rake fingers to process a respective one of the plurality of demodulated signals to generate a respective one of the corresponding plurality of soft symbol groups.
15. The apparatus of claim 11 , wherein:
the apparatus is operative within a wideband code division multiple access (WCDMA) communication system; and
each of the plurality of servicing cells operates in accordance with WCDMA.
16. The apparatus of claim 11 , wherein:
the apparatus is a wireless communication device; and
the wireless communication device is a laptop host computer, a personal digital assistant host, a personal computer host, or a cellular telephone host.
17. A method, comprising:
employing a radio frequency (RF) module to perform parallel processing of a plurality of paging broadcasts corresponding to a plurality of servicing cells thereby generating a plurality of demodulated signals;
operating a hardware accelerator module for processing the plurality of demodulated signals thereby generating a corresponding plurality of soft symbol groups such that each soft symbol group corresponds to one of the plurality of servicing cells;
storing each of the plurality of soft symbol groups in a memory module;
turning off the RF module after each of the plurality of soft symbol groups is stored in the memory module;
operating a host processor for performing serial Viterbi decoding of each of the plurality of soft symbol groups thereby generating a plurality of broadcast channel transport blocks such that each broadcast channel transport block corresponds to one of the plurality of servicing cells;
perform serial processing of the plurality of broadcast channel transport blocks thereby generating a plurality of system frame numbers, for use in timing synchronization with respect to the plurality of servicing cells, such that each frame number corresponds to one of the plurality of servicing cells;
turning on each of the RF module, the hardware accelerator module, the memory module, and the host processor module at a beginning of a wakeup period;
turning off the RF module after each of the plurality of soft symbol groups is stored in the memory module;
turning off the hardware accelerator module after the host processor module has generated the plurality of broadcast channel transport blocks; and
turning off the memory module and the host processor module after the plurality of system frame numbers is generated and output to a higher protocol layer module.
18. The method of claim 17 , wherein:
the plurality of paging broadcasts received via a Paging Indicator Channel (PICH).
19. The method of claim 17 , wherein:
the method is performed within a communication device that is operative within a wideband code division multiple access (WCDMA) communication system; and
each of the plurality of servicing cells operates in accordance with WCDMA.
20. The method of claim 17 , wherein:
the method is performed within a wireless communication device; and
the wireless communication device is a laptop host computer, a personal digital assistant host, a personal computer host, or a cellular telephone host.