Semiconductor on insulator devices containing permanent charge

1. A lateral semiconductor-on-insulator device comprising:

a body region connected to a drain region by a semiconductor-on-insulator region;

a gate electrode which is capacitively coupled to said body region;

a dielectric overlying said semiconductor-on-insulator region between the body region and the drain region; and

permanent charge, embedded in said dielectric, and having a density at least sufficient to cause depletion in the semiconductor-on-insulator region;

wherein said permanent charge comprises implanted ions; and

wherein at least some of said permanent charge overlies regions which are not overlaid by the gate electrode.

2. The lateral semiconductor-on-insulator device of claim 1 , further comprising

an insulator region beneath the semiconductor-on-insulator region, and

additional permanent charge embedded in the insulator region,

wherein said additional permanent charge at least partly depletes the semiconductor-on-insulator region.

3. The lateral semiconductor-on-insulator device of claim 2 , further comprising a trench gate.

4. The lateral semiconductor-on-insulator device of claim 2 , wherein said insulator is continuous across the entire device.

5. The lateral semiconductor-on-insulator device of claim 1 , further comprising a trench gate.

6. A lateral semiconductor-on-insulator device comprising:

a body region connected to a drain region by a semiconductor-on-insulator region;

a gate electrode which is capacitively coupled to the body region;

a dielectric overlying said semiconductor-on-insulator region between the body region and the drain region; and

permanent charge, embedded in said dielectric, and having a density at least sufficient to cause depletion in the semiconductor-on-insulator region;

wherein said permanent charge has a density sufficient to cause inversion in said semiconductor-on-insulator region;

wherein at least some of said permanent charge overlies regions which are not overlaid by the gate electrode; and

wherein said permanent charge comprises implanted ions.

7. A lateral semiconductor-on-insulator device comprising:

an n-type source region, separated from a drift region by a p-type body region;

said drift region separating said body region from a drain region;

a dielectric overlying said drift region;

said drift region overlying a buried dielectric layer; and

permanent charge, embedded at the interface between said dielectric and said drift region, and having a density at least sufficient to cause depletion in the drift region;

wherein said permanent charge comprises implanted ions.

8. The lateral semiconductor-on-insulator device of claim 7 , further comprising additional permanent charges embedded in said buried dielectric layer, and wherein said additional permanent charges at least partly deplete said drift region.

9. The lateral semiconductor-on-insulator device of claim 7 , wherein said drift region is n-type.

10. The lateral semiconductor-on-insulator device of claim 7 , wherein said drift region includes only a single conductivity type.

11. The lateral semiconductor-on-insulator device of claim 7 , further comprising a trench gate which controls conduction through part of said body region.

12. The lateral semiconductor device of claim 7 , further comprising a carrier source comprising a first-conductivity type source diffusion, and wherein said body is second-conductivity-type, and wherein the electrode lies within an isolation trench and is capacitively coupled to define a channel region which is interposed between said source diffusion and said drift region.

13. The semiconductor device of claim 7 , wherein said drift region is overlain by a dielectric layer which also contains ones of said permanent charges.

14. The semiconductor device of claim 7 , wherein said drift region is overlain by a dielectric layer which also contains ones of said permanent charges, and is also underlain by a buried dielectric layer which also contains ones of said permanent charges.

15. The semiconductor device of claim 7 , further comprising a tapered isolation trench.

16. A lateral semiconductor-on-insulator device comprising:

an n-type source region, separated from a drift region by a p-type body region;

said drift region separating said body region from a drain region;

a dielectric overlying said drift region;

said drift region overlying a buried dielectric layer; and

permanent charge, embedded at the interface between said dielectric and said drift region, and having a density at least sufficient to cause depletion in the drift region;

wherein said permanent charge has a density sufficient to cause inversion in said drift region; and

wherein said permanent charge comprises implanted ions.

17. The lateral semiconductor-on-insulator device of claim 16 , further comprising:

a gate electrode capacitively coupled to said body region;

wherein said permanent charge has a polarity which balances charge in nearby portions of said drift region when said drift region is depleted; and

wherein at least some of said permanent charge overlies regions which are not overlaid by the gate electrode.

18. The semiconductor device of claim 17 , wherein the buried dielectric layer contains ones of said permanent charges, and the drift region is laterally confined by a dielectric trench which also contains ones of said permanent charges.

19. The lateral semiconductor device of claim 17 , wherein the gate is capacitively coupled to define a channel region which is interposed between said source region and said drift region.

20. The semiconductor device of claim 17 , wherein said drift region is laterally confined by a dielectric trench which also contains ones of said permanent charges.