Method for making a semiconductor device having metal gate stacks

1. A method for making a semiconductor device having metal gate stacks comprising:

forming shallow trench isolation (STI) features in a silicon substrate, defining a first active region configured for a p-type field effect transistor (PFET) and a second active region configured for an n-type field effect transistor (NFET);

forming, on the silicon substrate, a hard mask having an opening to expose the silicon substrate within the first active region;

etching the silicon substrate through the opening of the hard mask to form a recess in the silicon substrate within the first active region;

growing a silicon germanium (SiGe) layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar;

forming metal gate material layers on the silicon substrate and the SiGe layer;

patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region;

forming an eSiGe source/drain (S/D) stressor distributed in both the SiGe layer and the silicon substrate within the first active region;

forming a first dielectric layer on the metal gate stack;

forming light-doped drain (LDD) features in the SiGe layer; and

forming a spacer on sidewall of the first dielectric layer prior to forming of the eSiGe S/D stressor.

2. The method of claim 1 , further comprising applying at least one of a pocket implantation and a halo implantation to the SiGe layer within the first active region prior to forming of the spacer.

3. A method for making a semiconductor device having metal gate stacks comprising:

forming shallow trench isolation (STI) features in a silicon substrate, defining a first active region configured for a p-type field effect transistor (PFET) and a second active region configured for an n-type field effect transistor (NFET);

forming, on the silicon substrate, a hard mask having an opening to expose the silicon substrate within the first active region;

etching the silicon substrate through the opening of the hard mask to form a recess in the silicon substrate within the first active region;

growing a silicon germanium (SiGe) layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar;

forming metal gate material layers on the silicon substrate and the SiGe layer;

patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and

forming an eSiGe source/drain (S/D) stressor distributed in both the SiGe layer and the silicon substrate within the first active region, wherein the forming of the metal gate material layers comprises:

forming a high k dielectric layer;

forming a metal layer on the high k dielectric layer; and

forming a conductive layer on the metal layer.

4. The method of claim 3 , wherein the conductive layer comprises doped polysilicon.

5. A method for making a semiconductor device having metal gate stacks comprising:

forming shallow trench isolation (STI) features in a silicon substrate, defining a first active region configured for a p-type field effect transistor (PFET) and a second active region configured for an n-type field effect transistor (NFET);

forming, on the silicon substrate, a hard mask having an opening to expose the silicon substrate within the first active region;

etching the silicon substrate through the opening of the hard mask to form a recess in the silicon substrate within the first active region;

growing a silicon germanium (SiGe) layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar;

forming metal gate material layers on the silicon substrate and the SiGe layer;

patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region;

forming an eSiGe source/drain (S/D) stressor distributed in both the SiGe layer and the silicon substrate within the first active region;

forming a thin silicon layer on the SiGe layer by epi growth; and

implementing an oxidization process to transform the thin silicon layer into a silicon oxide layer prior to forming of the metal gate material layers.

6. A method for making a semiconductor device having metal gate stacks comprising:

forming shallow trench isolation (STI) features in a silicon substrate, defining a first active region configured for a first p-type field effect transistor (PFET), a second active region configured for an n-type field effect transistor (NFET), and a third active region configured for a second PFET, wherein the third active region has a first dimension less than a second dimension of the first active region;

forming, on the silicon substrate, a hard mask having an opening that exposes the silicon substrate within the first active region;

etching the silicon substrate through the opening of the hard mask to form a recess in the silicon substrate within the first active region;

growing a silicon germanium (SiGe) layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second and third active regions are substantially coplanar;

forming metal gate material layers on the silicon substrate and the SiGe layer;

patterning the metal gate material layers to form a first metal gate stack on the SiGe layer within the first active region and a second metal gate stack on the silicon substrate within the third active region; and

forming first source/drain (S/D) features distributed in both the SiGe layer and the silicon substrate within the first active region and second S/D features distributed in the silicon substrate within the third active region.

7. The method of claim 6 , further comprising

forming a first dielectric layer on the first metal gate stack;

thereafter forming light-doped drain (LDD) features in the SiGe layer; and

forming a spacer on sidewall of the first dielectric layer prior to forming of the first and second S/D features.

8. The method of claim 6 , further comprising applying a halo ion implantation to the SiGe layer within the first active region prior to forming of the spacer.

9. The method of claim 6 , wherein the forming of the metal gate material layers comprising:

forming a high k dielectric layer;

forming a capping layer on the high k dielectric layer;

forming a metal layer on the high k dielectric layer; and

forming a conductive layer on the metal layer.

10. The method of claim 6 , further comprising:

forming a second hard mask on the silicon substrate patterned to have an opening exposing the silicon substrate within the second active region;

etching the silicon substrate within the second active region through the opening of second hard mask to form a second recess in the silicon substrate within the second active region; and

growing a silicon carbide (SiC) layer in the second recess such that the SiC layer and the SiGe layer are substantially coplanar.

11. The method of claim 10 , further comprising removing the second hard mask after the growing of the SiC layer.

12. The method of claim 10 , further comprising:

forming second metal gate layers on the SiC layer, the second metal gate layers are different from the metal gate layers in composition; and

patterning the second metal gate layers to form a second metal gate stack on the SiC layer within the second active region.