Semiconductor device and method of fabricating the same
A semiconductor device and method of fabricating the same, which forms a contact hole, a via hole or a via contact hole with multiple profiles with various taper angles. The semiconductor device includes a substrate, a thin film transistor formed on the substrate and having a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric, and a contact hole penetrating the gate insulating layer and the interlayer dielectric and exposing a portion of the semiconductor layer. The contact hole has a multiple profile in which an upper portion of the contact hole has a wet etch profile and a lower portion of the contact hole has at least one of the wet etch profile and a dry etch profile.
1. A semiconductor device, comprising:
a substrate;
a thin film transistor formed on the substrate and including a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric; and
a contact hole penetrating the gate insulating layer and the interlayer dielectric and exposing a portion of the semiconductor layer, and having a triple profile in which an upper portion of the contact hole has a wet etch profile, a middle portion of the contact hole has a high selectivity dry etch profile, and a lower portion of the contact hole has a high etch rate dry etch profile and a taper angle in a range of about 30° to about 70° .
2. The semiconductor device of claim 1 , wherein the wet etch profile in the upper portion of the contact hole has a taper angle in a range of about 5° to about 50° .
3. The semiconductor device of claim 1 , wherein the wet etch profile in the upper portion of the contact hole has a taper angle in a range of about 5° to about 35° .
4. The semiconductor device of claim 1 , wherein the high selectivity dry etch profile has a taper angle in a range of about 60 20 to about 90° .
5. The semiconductor device of claim 1 , wherein the high selectivity dry etch profile has a taper angle in a range of about 70° to about 90° .
6. The semiconductor device of claim 1 , wherein the high etch rate dry etch profile has a taper angle in a range of about 30° to about 50° .
7. A semiconductor device, comprising:
a substrate;
a thin film transistor (TFT) formed on the substrate and having a source electrode and a drain electrode;
a passivation layer and a planarization layer formed on the TFT; and
a via hole penetrating the passivation layer and the planarization layer and exposing a portion of either the source electrode and or the drain electrode, and having a triple profile in which an upper portion of the via hole has a wet etch profile, a middle portion of the hole has a high selectivity dry etch profile and a lower portion of the via hole has a high etch rate dry etch profile and a taper angle in a range of about 30° to about 70° .
8. The semiconductor device of claim 7 , wherein the wet etch profile in the upper portion of the via hole has a taper angle in a range of about 5° to about 50° .
9. The semiconductor device of claim 7 , wherein the wet etch profile in the upper portion of the via hole has a taper angle in a range of about 5° to about 35° .
10. The semiconductor device of claim 7 , wherein the high selectivity dry etch profile has a taper angle in a range of about 60° to about 90° .
11. The semiconductor device of claim 7 , wherein the high selectivity dry etch profile has a taper angle in a range of about 70° to about 90° .
12. The semiconductor device of claim 7 , wherein the high etch rate dry etch profile has a taper angle in a range of about 30° to about 50° .
13. A semiconductor device, comprising:
a substrate;
a semiconductor layer, a gate insulating layer, and a gate electrode formed on the substrate;
a planarization layer formed on the substrate; and
a via contact hole penetrating the planarization layer and the gate insulating layer and exposing a portion of the semiconductor layer, and having a triple profile in which an upper portion of the via contact hole has a wet etch profile, a middle portion of the via contact hole has a high selectivity dry etch profile and a lower portion of the via contact hole has a high etch rate dry etch profile and a taper angle in a range of about 30° to about 70° .
14. The semiconductor device of claim 13 , wherein a metal interconnection line or a pixel electrode contacts the exposed portion of the semiconductor layer through the via contact hole.