Design methodology for MuGFET ESD protection devices
A method for manufacturing a MuGFET ESD protection device having a given layout by means of a given manufacturing process, the method comprising selecting multiple interdependent layout and process parameters of which a first set are fixed by said manufacturing process and a second set are variable, selecting multiple combinations of possible layout and process parameter values which meet predetermined ESD constraints; determining an optimum value for at least one other parameter in view of a predetermined design target apart from the predetermined ESD constraints; determining values for fin width (W fin ), gate length (L G ) and number of fins (N) on the basis of the optimum value; and manufacturing said MuGFET ESD protection device using the given manufacturing and process values.
1. A method for manufacturing a multi-gate field-effect transistor (MuGFET) electrostatic discharge (ESD) protection device having a given layout by means of a given manufacturing process, comprising:
selecting multiple combinations of possible layout and process parameter values including at least fin width, gate length, and number of fins, each of said combinations being selected to meet predetermined ESD constraints for said MuGFET ESD protection device,
determining multiple values for at least one other parameter having a predetermined relationship with said fin width, gate length, and number of fins,
determining for said at least one other parameter an optimum value in view of a predetermined design target apart from said predetermined ESD constraints,
determining parameter values for said fin width, gate length, and number of fins substantially on the basis of the optimum value determined of the one other parameter, and
manufacturing said MuGFET ESD protection device substantially using said optimum value of the at least one other parameter and the determined parameter values for fin width, gate length, and number of fins.
2. The method according to claim 1 , wherein the optimum value is determined by interpolation while taking into account said predetermined ESD constraints.
3. The method according to claim 1 , wherein said selecting step includes selecting multiple combinations of possible layout and process values further including: a distance between landing pad and gate, an overlap amount of the gate past the fins, and a fin-to-fin spacing.
4. The method according to claim 1 , wherein said selecting step includes selecting multiple combinations of possible layout and process values further including: strain, well implants, selective epitaxial growth, silicide blocking, and thickness of buried oxide.
5. The method according to claim 1 , wherein said selecting step includes selecting multiple combinations of possible layout and process values further including: a contact area and a folding factor of said device.
6. The method according to claim 1 , wherein said at least one other parameter comprises is selected from the group consisting of: overall area of said device, maximum voltage, maximum voltage during voltage overshoot, leakage current, and capacity.
7. The method according to claim 1 , wherein said MuGFET ESD device is a metal oxide semiconductor (MOS) clamp provided for operating either in parasitic bipolar or active MOS diode mode.
8. The method according to claim 7 , wherein said MOS clamp is designed for operating in bipolar mode, wherein the predetermined ESD constraints comprise an ESD stress which the device must be able to sustain, while meeting a given leakage specification and without exceeding a given maximum voltage, and wherein said predetermined design target is a minimum overall area of said MOS clamp.
9. The method according to claim 8 , wherein the given maximum voltage is the gate oxide breakdown voltage.
10. The method according to claim 7 , wherein said MOS clamp is designed for operating in MOS diode mode, wherein the predetermined ESD constraints comprise an ESD stress which the device must be able to sustain, while meeting a given leakage specification and without exceeding a given maximum voltage, and wherein said predetermined design target is a minimum overall area and a minimum number of fins of said MOS clamp.
11. The method according to claim 10 , wherein the given maximum voltage is the gate oxide breakdown voltage.
12. The method according to claim 1 , wherein said MuGFET ESD device is a gated diode and said predetermined design target is a minimum parasitic capacity.
13. The method according to claim 1 , wherein said MuGFET ESD device is a Grounded-Gate-NMOS MuGFET device.