IP Library Granted Patent US 7,951,630
Granted Patent B2
US 7,951,630 · App. 12/442,617 · Granted May 31, 2011

Method of fabricating light emitting diode chip

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,951,630
App. No.
12/442,617
Granted
May 31, 2011
Kind
B2
Abstract

The present invention provides a method of fabricating a light emitting diode chip having an active layer between an N type semiconductor layer and a P type semiconductor layer. The method comprises the steps of preparing a substrate; laminating the semiconductor layers on the substrate, the semiconductor layers having the active layer between the N type semiconductor layer and the P type semiconductor layer; and forming grooves on the semiconductor layers laminated on the substrate until the substrate is exposed, whereby inclined sidewalls are formed by the grooves in the semiconductor layers divided into a plurality of chips. According to embodiments of the present invention, a sidewall of a semiconductor layer formed on a substrate of a light emitting diode chip is inclined with respect to the substrate, whereby its directional angle is widened as compared with a light emitting diode chip without such inclination. As the directional angle of the light emitting diode chip is wider, when a white light emitting device is fabricated using the light emitting diode chip and a phosphor, light uniformity can be adjusted even though the phosphor is not concentrated at the center of the device. Thus, the overall light emitting efficiency can be enhanced by reducing a light blocking phenomenon caused by the increased amount of the phosphor distributed at the center portion.

Claims (8)

1. A method of fabricating a light emitting diode chip having an active layer between an N type semiconductor layer and a P type semiconductor layer, the method comprising the steps of:

preparing a substrate;

laminating the active layer, N type semiconductor layer, and P type semiconductor layers on the substrate, such that the active layer is disposed between the N type semiconductor layer and the P type semiconductor layer;

forming grooves through the laminated layers, such that the layers are divided into individual chips, the substrate is exposed between the chips, and sidewalls of the grooves are formed by inclined sidewalls of the laminated layers;

performing a scribing process on the substrate; and

applying a mechanical force to the scribed substrate to break the scribed substrate and thereby separate the individual chips from each other.

2. The method as claimed in claim 1 , wherein the forming of the grooves comprises using a blade having an inclined edge to form the grooves.

3. The method as claimed in claim 2 , wherein the blade edge has an edge angle in a range of between 50° and 150°.

Assignments (2)
CHANGE OF NAME Recorded Apr 21, 2014
From: SEOUL OPTO DEVICE CO., LTD
To: SEOUL VIOSYS CO., LTD
Reel/Frame 032723/0126 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 25, 2009
From: LEE, JUN HEE; KIM, JONG KYU; YOON, YEO JIN
To: SEOUL OPTO DEVICE CO., LTD.
Reel/Frame 022448/0012 →