Device and system for reducing noise induced errors
View Patent ↗A method and a device for reducing noise induced errors. The device includes: a latch that includes a latch input node; a voltage limiting transfer circuit connected between a first input node and between the latch; wherein the voltage limiting transfer circuit is adapted to selectively transfer an input signal from the first input node to the latch during transfer mode; and to prevent a transfer of an input signal from the first input node to the latch by limiting voltage levels developed in the voltage limiting transfer circuit to a predefined range.
1. A device for reducing noise induced errors, the device comprises:
a latch that comprises a latch input node; and
a voltage limiting transfer circuit coupled between a first input node and the latch, the voltage limiting transfer circuit adapted to selectively transfer an input signal from the first input node to the latch during transfer mode, and to prevent a transfer of an input signal from the first input node to the latch by limiting voltage levels developed in the voltage limiting transfer circuit to a predefined range, wherein the voltage limiting transfer circuit comprises:
a first transistor;
a second transistor; and
a third transistor, wherein:
a source of the first and second transistors are coupled to a supply source;
gates of the first and second transistors are coupled to each other and are adapted to receive an inverted scan enable signal;
a drain of the first transistor is coupled to a first intermediate node;
a drain of the third transistor is coupled to a second intermediate node;
a drain of the second transistor is coupled to a source of the third transistor; and
a gate of the third transistor receives an inverted clock signal.
2. The device according to claim 1 further comprising multiple additional transistors, adapted to perform an inversion operation.
3. The device according to claim 1 wherein the voltage limiting transfer circuit is faster than an inverter coupled to a transfer gate.
4. The device according to claim 1 wherein the input signal is a clock signal and wherein an output signal of the device is a gated clock signal.
5. The device according to claim 1 wherein the voltage limiting transfer circuit further comprises:
a first NMOS transistor coupled between the first input node and the first intermediate node;
an output NMOS transistor coupled between the first intermediate node and the input node of the latch; and
a pull up circuit coupled to the first intermediate node.
6. The device according to claim 1 wherein the voltage limiting transfer circuit further comprises:
a first PMOS transistor coupled between the first input node and the second intermediate node;
an output PMOS transistor coupled between the second intermediate node and the input node of the latch; and
a pull down circuit coupled to the second intermediate node.
7. The device according to claim 1 wherein the voltage limiting transfer circuit further comprises at least one pull up circuit and at least one pull down circuit adapted to limit voltage levels developed in the voltage limiting transfer circuit when the voltage limiting transfer circuit is in a non-transfer mode.
8. The device according to claim 7 wherein the voltage limiting transfer circuit further comprises:
a first NMOS transistor coupled between the first input node and the first intermediate node;
an output NMOS transistor coupled between the first intermediate node and the input node of the latch; and
a pull up circuit coupled to the first intermediate node.
9. The device according to claim 7 wherein the voltage limiting transfer circuit further comprises:
a first PMOS transistor coupled between the first input node and the second intermediate node;
an output PMOS transistor coupled between the second intermediate node and the input node of the latch; and
a pull down circuit coupled to the second intermediate node.
10. The device according to claim 7 wherein the pull down circuit is adapted to limit voltage levels developed at the second intermediate node to negative voltages, the second intermediate node coupled to an input of an output PMOS transistor of the voltage limiting transfer circuit.
11. The device according to claim 7 wherein the pull up circuit is adapted to limit voltage levels developed at the first intermediate node to positive voltages, the first intermediate node coupled to an input of an output NMOS transistor of the voltage limiting transfer circuit.
12. The device according to claim 11 wherein the pull down circuit is adapted to limit voltage levels developed at the second intermediate node to negative voltages, the second intermediate node coupled to an input of an output PMOS transistor of the voltage limiting transfer circuit.
13. A method for reducing noise induced errors, the method comprises:
receiving an input signal;
providing to a latch, by a voltage limiting transfer circuit, a latch input signal representative of the received input signal, during a transfer mode; and
preventing a transfer of the input signal towards the latch, during a non-transfer mode, by limiting voltage levels developed in the voltage limiting transfer circuit to a predefined range, the voltage limiting transfer circuit comprising:
a first transistor;
a second transistor; and
a third transistor, wherein:
a source of the first and second transistors are coupled to a supply source;
gates of the first and second transistors are coupled to each other and are adapted to receive an inverted scan enable signal;
a drain of the first transistor is coupled to a first intermediate node;
a drain of the third transistor is coupled to a second intermediate node;
a drain of the second transistor is coupled to a source of the third transistor; and
a gate of the third transistor receives an inverted clock signal.
14. The method according to claim 13 wherein the preventing comprises utilizing at least one pull up circuit and at least one pull down circuit.
15. The method according to claim 14 wherein the preventing comprises limiting voltage levels developed at the first intermediate node to positive voltages, the first intermediate node coupled to an input of an output NMOS transistor of the voltage limiting transfer circuit.
16. The method according to claim 15 wherein the preventing comprises limiting voltage levels developed at the second intermediate node to negative voltages, the second intermediate node coupled to an input of an output PMOS transistor of the voltage limiting transfer circuit.
17. The method according to claim 13 wherein the providing includes inverting the input signal during a transfer gate node.
18. The method according to claim 13 further comprising generating a gated clock signal.
19. The method according to claim 13 wherein the voltage limiting transfer circuit further comprises:
a first NMOS transistor coupled between the first input node and the first intermediate node;
an output NMOS transistor coupled between the first intermediate node and the input node of the latch; and
a pull up circuit coupled to the first intermediate node.
20. The method according to claim 13 wherein the voltage limiting transfer circuit further comprises:
a first PMOS transistor coupled between the first input node and the second intermediate node;
an output PMOS transistor coupled between the second intermediate node and the input node of the latch; and
a pull down circuit coupled to the second intermediate node.