Semiconductor device including semiconductor chip and sealing material
View Patent ↗A semiconductor device includes at least bonding wires between electrode pads on a main surface of a semiconductor chip and connection pads on a wiring board. The wires form loop shapes from the electrode pads of the semiconductor chip. The semiconductor device also includes at least forming flat parts on the loop-shaped wires, and using a sealing material to seal the semiconductor chip such as to bury the flat parts.
1. A semiconductor device comprising:
a wiring board;
a semiconductor chip that is disposed on one face side of the wiring board; and
wires that form loop shapes from electrode pads of the semiconductor chip between the electrode pads on a main surface of the semiconductor chip and connection pads on the wiring board,
wherein the wires comprise flat parts that are buried by a sealing material,
wherein the sealing material comprises a primary sealant and a secondary sealant, and
the flat parts are at an interface between the primary sealant and the secondary sealant.
2. The semiconductor device according to claim 1 , wherein the primary sealant comprises one or more indentations that are filled with the secondary sealant.
3. A semiconductor device comprising:
a wiring board including a first surface and a plurality of connection pads formed on the first surface;
a semiconductor chip including an upper surface and a plurality of electrode pads formed on the upper surface, and mounted on the first surface of the wiring board;
a plurality of bonding wires electrically connecting the connection pads of the wiring board to the electrode pads of the semiconductor chip, respectively, each of the bonding wires including a flat part that is substantially parallel to the upper surface of semiconductor chip, and the flat part of selected one of the bonding wires is disposed substantially coplanar with the flat part of another of bonding wires;
a first resin layer provided between the upper surface of the semiconductor chip and the flat part of the selected one of the bonding wires; and
a second resin layer provided on the first resin layer, at least a part of the flat part of the selected one of the bonding wires being disposed between the upper surface and the second resin layer.
4. The semiconductor device according to claim 3 , wherein the first resin layer includes one or more indentations that are filled with the second resin layer.
5. The semiconductor device according to claim 3 , wherein the plurality of electrode pacts are disposed on a position that is a periphery of the upper surface of the semiconductor chip.
6. The semiconductor device according to claim 3 , wherein the first resin layer and the second resin layer are same material.
7. The semiconductor device according to claim 3 , wherein the first resin layer and the second resin layer are a thermosetting resin.
8. The semiconductor device according to claim 3 , wherein the semiconductor chip includes a lower surface opposed to the upper surface, and the semiconductor chip mounted on the first surface of the wiring board so that the lower surface of the semiconductor chip faces the wiring board.
9. The semiconductor device according to claim 3 , wherein the first resin layer includes one or more indentations that are filled with the second resin layer.
10. The semiconductor device according to claim 3 , wherein the plurality of electrode pads are disposed on a position that is a periphery of the upper surface of the semiconductor chip.
11. The semiconductor device according to claim 3 ; Wherein the first resin layer is extended from the flat part of selected one of the bonding wires to the flat part of another of the bonding wires.
12. The semiconductor device according to claim 3 , wherein at least a part of the selected one of the bonding wires are disposed between the upper surface and the second resin layer.
13. The semiconductor device according to claim 3 , wherein the semiconductor chip includes a lower surface opposed to the upper surface, and the semiconductor chip mounted on the first surface of wiring board so that the lower surface of the semiconductor chip faces the wiring board.
14. A semiconductor device comprising:
a wiring board including a first surface and a plurality of connection pads provided on the first surface;
a semiconductor chip including an upper surface and a plurality of electrode pads provided on the upper surface, and mounted over the first surface of the wiring board;
a plurality of bonding wires electrically coupling the connection pads to the electrode pads, respectively, each of the plurality of bonding wires including a flat part, and each of the flat parts substantially parallel to the upper surface of the semiconductor chip;
a first resin layer provided between the upper surface of the semiconductor chip and the flat parts of the bonding wires; and
a second resin layer provided on the first resin layer.
15. A semiconductor device comprising:
a wiring board;
a semiconductor chip that is disposed on one face side of the wiring board; and
wires that form loop shapes between electrode pads on a main surface of the semiconductor chip and connection pads on the wiring board, a top surface of the electrode pads being above a top surface of the connection pads,
wherein the wires comprise flat parts that are buried by a sealing material,
wherein the sealing material comprises a primary sealant and a secondary sealant, and
the flat parts are at an interface between the primary sealant and the secondary sealant.
16. The semiconductor device according to claim 15 , wherein the wires are formed loop shapes from the electrode pads of the semiconductor chip to the connection pads of the wiring board.
17. The semiconductor device according to claim 15 , wherein the primary sealant comprises one or more indentations that are filled with the secondary sealant.
18. The semiconductor device according to claim 15 , wherein the primary sealant and the secondary sealant area thermosetting resin.