Semiconductor integrated circuit device with reduced leakage current
View Patent ↗The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.
1. A method for manufacturing a semiconductor device including a pair of N-channel type first and second MIS transistors, the method comprising:
providing a pair of first and second P-type wells in which a first and a second MIS transistor is to be formed,
forming a gate isolation thin film and a gate electrode on each of the first and second P-type wells
implanting phosphorus to the first P-type well,
implanting arsenic to the second P-type well,
forming side walls for the gate electrode after completion of implantation of phosphorus and arsenic, and
implanting arsenic to each of the first and the second P-type wells after completion of forming of the side walls.
2. The method according to claim 1 , wherein:
2-1: the semiconductor device further comprises an SRAM memory cell and a control circuit for controlling the SRAM memory cell,
2-2: the first MIS transistor comprises an N-channel type MIS transistor within the SRAM memory cell, and
2-3: the second MIS transistor comprises an N-channel type MIS transistor within the controlling circuit.
3. The method according to claim 2 , wherein:
3-1: the semiconductor device further comprises an input/output circuit including a third MIS transistor,
3-2: a third P-type well is arranged to be formed during forming of the first and the second P-type well,
3-3: the gate isolation thin film and the gate electrode are configured to be formed on the third P-type well,
3-4: arsenic is implanted into the third P-type well after completion of forming of the side walls, and
3-5: both phosphorus and arsenic are configured to be implanted into the third P-type well before forming of the side walls.