Semiconductor device and method of manufacturing the same
A semiconductor device that enables placement of a line or the like under a fuse without any additional step and a method of manufacturing the same are provided. The semiconductor device includes a plurality of first capacitor holes made in an insulating layer, a capacitor formed in the first capacitor holes, a DRAM cell made up of the capacitor and a transistor coupled to the capacitor, a plurality of second capacitor holes made in the insulating layer, and a fuse formed between the second capacitor holes.
1 . A semiconductor device which includes a dynamic random access memory (DRAM) cell and a fuse comprising:
an insulating layer having a plurality of first capacitor holes and a plurality of second capacitor holes;
a capacitor function as the DRAM cell formed in the first capacitor holes; and
a fuse formed between the second capacitor holes.
2 . The semiconductor device according to claim 1 , wherein an interval between the second capacitor holes is larger than an interval between the first capacitor holes.
3 . The semiconductor device according to claim 1 ,
wherein the capacitor includes a lower electrode and an upper electrode, and
the fuse includes at least one of a first conductive layer in the same layer as the lower electrode of the capacitor or a second conductive layer in the same layer as the upper electrode of the capacitor.
4 . The semiconductor device according to claim 1 ,
wherein the capacitor comprises a lower electrode and an upper electrode, and
the fuse comprises a first conductive layer which is the same layer of the lower electrode of the capacitor, a second conductive layer which is the same layer of the upper electrode of the capacitor, and a third conductive layer that connects the first conductive layer and the second conductive layer,
wherein the first conductive layer is formed along internal surfaces of the second capacitor holes, and the second conductive layer is formed in the second capacitor hole and between the second capacitor holes, and
wherein a fuse cut portion is the second conductive layer formed between the second capacitor holes.
5 . The semiconductor device according to claim 4 , wherein the third conductive layer is a contact plug.
6 . The semiconductor device according to claim 1 ,
wherein the capacitor comprises a lower electrode and an upper electrode, and
the fuse comprises a first conductive layer which is the same layer of the lower electrode of the capacitor, a second conductive layer which is the same layer of the upper electrode of the capacitor, and a third conductive layer that connects the first conductive layer and the second conductive layer,
wherein a first conductive layer is formed on internal surfaces of the second capacitor holes and between the second capacitor holes and a second conductive layer is formed above the first conductive layer on internal surfaces of the second capacitor holes and between the second capacitor holes, and
wherein a fuse cut portion is the first conductive layer and the second conductive layer formed between the second capacitor holes.
7 . The semiconductor device according to claim 1 , comprising:
wherein the capacitor comprises a lower electrode and an upper electrode, and
the fuse comprises a first conductive layer which is the same layer of the lower electrode of the capacitor, a second conductive layer which is the same layer of the upper electrode of the capacitor, and a third conductive layer that connects the first conductive layer and the second conductive layer,
wherein a first conductive layer is formed on internal surfaces of the second capacitor holes and between the second capacitor holes and a second conductive layer is formed above the first conductive layer inside the second capacitor holes, and
wherein a fuse cut portion is the first conductive layer formed between the second capacitor holes.
8 . The semiconductor device according to claim 4 , wherein the first conductive layer is a lead line of the fuse.
9 . The semiconductor device according to claim 1 , wherein adjacent fuses are disposed in a staggered arrangement.
10 . A method of manufacturing a semiconductor device comprising:
forming an insulating layer on a semiconductor substrate;
making first capacitor holes and second capacitor holes in the insulating layer;
forming a capacitor in the first capacitor holes; and
forming a fuse by forming a conductive layer between the second capacitor holes.
11 . The method of manufacturing a semiconductor device according to claim 10 , wherein
the first capacitor holes and the second capacitor holes are made in the same step, and
the fuse is formed in the same step as forming at least one of an upper electrode and a lower electrode of the capacitor.