Dram having deeper source drain region than that of an logic region

1. A semiconductor device having a DRAM region and a logic region embedded together therein, comprising:

a substrate having said DRAM region and said logic region formed therein;

a first transistor formed in said DRAM region of said substrate, and having a first source/drain region containing arsenic and phosphorus as impurities; and

a second transistor formed in said logic region of said substrate, and having a second source/drain region containing at least arsenic as an impurity,

wherein each of said first source/drain region and said second source/drain region of said substrate has a silicide layer respectively formed in the surficial portion thereof, and

said first source/drain region has a junction depth which is determined by phosphorus and is deeper than the junction depth of said second source/drain region.

2. The semiconductor device as claimed in claim 1 ,

wherein said first source/drain region has the peak concentration of arsenic substantially equal to the peak concentration of arsenic of said second source/drain region.

3. The semiconductor device as claimed in claim 1 ,

wherein said second source/drain region contains phosphorus.

4. The semiconductor device as claimed in claim 1 ,

wherein said first source/drain region has the peak concentration of phosphorus larger than the peak concentration of phosphorus of said second source/drain region.

5. The semiconductor device as claimed in claim 2 ,

wherein said first source/drain region has the peak concentration of phosphorus larger than the peak concentration of phosphorus of said second source/drain region.

6. The semiconductor device as claimed in claim 3 ,

wherein said first source/drain region has the peak concentration of phosphorus larger than the peak concentration of phosphorus of said second source/drain region.

7. A method of manufacturing a semiconductor device having a DRAM region and a logic region embedded together therein, the method comprising:

forming a gate electrode in each of said DRAM region and said logic region formed in a substrate;

introducing impurity ions by ion implantation respectively into said logic region and said DRAM region, while using said gate electrodes as a mask;

allowing said impurities to diffuse by annealing, to thereby form a first source/drain region and a second source/drain region respectively in said DRAM region and said logic region; and

forming a silicide layer in the surficial portion of each of said first source/drain region and said second source/drain region,

wherein in said introducing said impurities by ion implantation, arsenic and phosphorus are introduced into said DRAM region as said impurities, and at least arsenic is introduced into said logic region as the impurity, so that the junction depth in said first source/drain region is determined by phosphorus, and is made deeper than the junction depth of said second source/drain region.

8. The method of manufacturing a semiconductor device as claimed in claim 7 ,

wherein said first source/drain region has the peak concentration of arsenic substantially equal to the peak concentration of arsenic of said second source/drain region.

9. The method of manufacturing a semiconductor device as claimed in claim 7 ,

wherein said introducing said impurities by ion implantation includes:

introducing at least arsenic as said impurity into said logic region by ion implantation, while masking said DRAM region, and while using said gate electrode in said logic region as a mask; and

introducing arsenic and phosphorus as said impurities into said DRAM region by ion implantation, while masking said logic region, and while using said gate electrode in said DRAM region as a mask.

10. The method of manufacturing a semiconductor device as claimed in claim 7 ,

wherein in said introducing said impurities by ion implantation, phosphorus is introduced also into said logic region as said impurity by ion implantation, and phosphorus is introduced into said DRAM region at an ion implantation energy larger than an ion implantation energy at which phosphorus is introduced into said logic region.

11. The method of manufacturing a semiconductor device as claimed in claim 7 ,

wherein in said introducing said impurities by ion implantation, phosphorus is introduced also into said logic region as said impurity, and phosphorus is introduced into said DRAM region at a dose higher than a dose at which phosphorus is introduced into said logic region.

12. The method of manufacturing a semiconductor device as claimed in claim 7 ,

wherein said introducing said impurities by ion implantation includes:

introducing at least arsenic as said impurity by ion implantation, simultaneously into said DRAM region and said logic region; and

selectively introducing phosphorus as said impurity into said DRAM region by ion implantation, while masking said logic region, and while using said gate electrode in said DRAM region as a mask.

13. The method of manufacturing a semiconductor device as claimed in claim 12 ,

wherein in said introducing at least arsenic as said impurity by ion implantation, simultaneously into said DRAM region and said logic region, also phosphorus is introduced by ion implantation as said impurity.