Clock gating circuit having a selector that selects one of a control signal and a scan signal
View Patent ↗Provided is a clock gating circuit which receives a first clock signal and controls an output of a second clock signal corresponding to the first clock signal in response to a control signal. The clock gating circuit includes: a first latch that latches a signal value of the control signal in synchronization with the first clock signal; an AND that receives the first clock signal and controls an output of the second clock signal in response to an output signal of the first latch; and a second latch that latches a signal value of the output signal of the first latch in synchronization with the first clock signal, and outputs a latched value. This enables execution of a scan test with a simple circuit configuration.
1. A clock gating circuit which receives a first clock signal and controls an output of a second clock signal corresponding to the first clock signal in response to a control signal, the clock gating circuit comprising:
a first latch that latches a signal value of the control signal in synchronization with the first clock signal;
a first gate that receives the first clock signal and controls the output of the second clock signal in response to an output signal of the first latch;
a second latch that latches a signal value of the output signal of the first latch in synchronization with the first clock signal, and outputs a latched value; and
a second gate that controls the output of the second latch in response to a test enable signal and the first clock signal,
wherein the first latch and the second latch form a scan path for a scan test.
2. The clock gating circuit according to claim 1 , wherein each of the first latch and the second latch latches a signal value of an input signal at a different signal level of the first clock signal.
3. The clock gating circuit according to claim 1 , wherein the second gate controls an output of the first clock signal to the second latch in response to the test enable signal for switching between a normal operation mode and a scan test mode.
4. The clock gating circuit according to claim 1 , wherein the first gate controls the output of the second clock signal in response to the output signal of the first latch and the test enable signal for switching between a normal operation mode and a scan test mode.
5. The clock gating circuit according to claim 1 , further comprising a selector that selects one of the control signal and a scan signal for observing an operation of the first latch, and supplies a selected signal to the first latch.
6. The clock gating circuit according to claim 1 , wherein the clock gating circuit serves as a macro cell.
7. The clock gating circuit according to claim 1 , wherein the first gate comprises an AND gate.
8. The clock gating circuit according to claim 1 , wherein the second gate comprises an AND gate.
9. The clock gating circuit according to claim 1 , further comprising a third gate that controls an output of the first gate in response to a test enable signal and the output signal of the first latch.
10. The clock gating circuit according to claim 9 , wherein the first gate receives an output of the second gate and a clock signal and outputs to the second clock signal.
11. The clock gating circuit according to claim 9 , wherein the third gate comprises an OR gate.
12. A clock gating circuit which receives a first clock signal and controls an output of a second clock signal corresponding to the first clock signal in response to a control signal, the clock gating circuit comprising:
a first gate that receives the first clock signal and a test enable signal;
a first latch that latches a signal value of the control signal in synchronization with the first clock signal;
a second latch that latches a signal value of the output signal of the first latch in synchronization with an output of the first gate, and outputs a latched value;
a second gate that controls an output of the first clock signal corresponding to the first latch in response to the test enable signal; and
a third gate that controls an output of the second clock signal in response to an output of the second gate and the first clock signal.
13. A clock gating circuit which receives a first clock signal and controls an output of a second clock signal corresponding to the first clock signal in response to a control signal, the clock gating circuit comprising:
a first latch that latches a signal value of the control signal in synchronization with the first clock signal;
a first gate that controls an output of the first clock signal corresponding to the first latch in response to the test enable signal;
a second gate that controls the output of the second clock signal in response to an output of the first gate and the first clock signal; and
a second latch that latches a signal value of the output signal of the first latch in synchronization with the first clock signal, and outputs a latched value.
14. The clock gating circuit according to claim 13 , further comprising a third gate that controls the output of the second latch in response to a test enable signal and the first clock signal.