Address detection circuit and address detection method
View Patent ↗An address detection circuit includes a correction signal generator that generates a plurality of timing correction signals based on an ADIP (Address In Pre-groove) signal that is read out from a wobble of an optical disk, the timing correction signals having different cycles with each other, a correction signal selector that selects one of the timing correction signals generated by the correction signal generator and outputs the selected signal, and a timing corrector that outputs a data address detected based on a data signal that is read out from a data track of the optical disk at a timing in accordance with the timing correction signal transmitted from the correction signal selector.
1. An address detection circuit comprising:
a correction signal generator that generates a plurality of timing correction signals based on an ADIP (Address In Pre-groove) signal that is read out from a wobble of an optical disk, the timing correction signals having different cycles with each other;
a correction signal selector that selects one of the timing correction signals generated by the correction signal generator and outputs the selected signal; and
a timing corrector that outputs a data address detected based on a data signal that is read out from a data track of the optical disk at a timing in accordance with the timing correction signal transmitted from the correction signal selector.
2. The address detection circuit according to claim 1 , further comprising:
a first data address hold circuit that holds the data address and outputs the data address to the timing corrector at a timing in accordance with a data synchronizing signal generated from the data signal.
3. The address detection circuit according to claim 2 , wherein the timing corrector comprises:
a second data address hold circuit that holds and outputs the data address; and
a controller that transfers the data address held in the first address hold circuit to the second data address hold circuit at a timing in accordance with the timing correction signal transmitted from the correction signal selector.
4. The address detection circuit according to claim 2 , further comprising:
a data address detector that detects the data address from the data signal; and
a data synchronizing signal generator that generates the data synchronizing signal from the data signal.
5. The address detection circuit according to claim 1 , wherein the correction signal generator comprises:
a plurality of judgment units that judge whether each cycle of ADIP synchronizing signals, which are detected from the ADIP signal, is a certain cycle; and
a plurality of correction signal generation units that generate the timing correction signals in accordance with the judgment results by the judgment units.
6. The address detection circuit according to claim 5 , further comprising:
an ADIP address hold circuit that holds an ADIP address detected from the ADIP signal, wherein
the correction signal generator also generates a timing signal that determines a timing at which the ADIP address hold circuit receives the ADIP address.
7. The address detection circuit according to claim 6 , wherein the correction signal generator comprises:
a first judgment unit that judges whether a cycle of a first ADIP synchronizing signal generated from the ADIP signal is a predetermined cycle;
a second judgment unit that judges whether a cycle of a second ADIP synchronizing signal generated from the ADIP signal is a predetermined cycle;
a third judgment unit that judges continuity of the ADIP address supplied to the ADIP address hold circuit;
a first correction signal generation unit that generates a first timing correction signal based on the judgment result of the first judgment unit;
a timing signal generation unit that generates the timing signal based on the judgment result of the second judgment unit; and
a second correction signal generation unit that receives and holds the ADIP address based on the judgment result of the third judgment unit and generates a second timing correction signal based on the holding ADIP address.
8. The address detection circuit according to claim 6 , further comprising:
an ADIP address detector that detects the ADIP address from the ADIP signal; and
a second synchronizing signal generator that generates the synchronizing signal from the ADIP signal.
9. An address detection method that detects an address indicating a position on an optical disk, the method comprising:
generating a plurality of timing correction signals based on an ADIP (Address In Pre-groove) signal that is read out from a wobble of the optical disk, the timing correction signals having different cycles with each other;
selecting one of the plurality of timing correction signals; and
outputting a data address that is detected based on a data signal that is read out from a data track of the optical disk at a timing in accordance with the selected timing correction signal.
10. The address detection method according to claim 9 , further comprising holding and outputting the data address at a timing in accordance with a data synchronizing signal generated from the data signal.
11. The address detection method according to claim 10 , further comprising transferring the data address that is held in a first address hold unit to a second data address hold unit at a timing in accordance with the timing correction signal that is selected.