Method circuit and system for receiving and processing multi-frames
Disclosed is a receiver containing a receive chain, a shared buffer, a decoder circuit, and an output interface. The receive chain may be adapted to receive and demodulate a data frame bearing signal received at one or more carrier frequencies. The receive chain may be further adapted to store demodulated data in a shared buffer. The decoder circuit may be adapted to read received data from the shared buffer, process the received data and write the decoded data back to the shared buffer. The output interface may be adapted to read the processed data and to provide read data to one or more external data sink circuits or applications.
1 . A receiver comprising:
a receive chain adapted to receive and demodulate a data frame bearing signal received at one or more carrier frequencies, said receiver further adapted to store demodulated data in a shared buffer;
a decoder circuit adapted to read received data from the shared buffer, process the received data and write the decoded data back to the shared buffer; and
an output interface adapted to read the processed data and to provide read data to one or more external data sink circuits or applications.
2 . The receiver according to claim 1 , wherein said decoder circuit is further adapted to reconstruct data frames from the received data.
3 . The receiver according to claim 2 , wherein said decoder circuit is further adapted to concurrently reconstruct two or more the data frames.
4 . The receiver according to claim 1 , wherein said decoder circuit is further adapted to include a byte deinterleaver and an error correcting decoder.
5 . The receiver according to claims 4 , wherein said decoder is adapted to read a complete data frame for deinterleaving and decoding.
6 . The receiver according to claim 4 , wherein said decoder circuit is further adapted to read a complete burst of the data frame bearing signal for deinterleaving and decoding.
7 . The receiver according to claim 1 , further adapted to power cycle said receive chain when the data frame bearing signal is received in bursts.
8 . The receiver according to claim 7 , further adapted to power down said receive chain in between the bursts of signal reception.
9 . The receiver according to claim 1 , further adapted to power cycle said decoder circuit when the data frame bearing signal is received in bursts.
10 . The receiver according to claim 9 , further adapted to power down said decoder circuit during the bursts of signal reception.
11 . The receiver according to claim 1 , wherein said shared buffer is further adapted to contain a plurality of independently accessible segments.
12 . The receiver according to claim 11 , wherein the segments of said shared buffer are further adapted to be accessible to one circuit or application at each clock interval.
13 . The receiver according to claim 11 , wherein said shared buffer includes at least one dynamically allocated memory segment and at least one statically allocated memory segment.
14 . The receiver according to claim 13 , wherein said shared buffer is further adapted to fill chunks of the dynamically allocated memory with fragments of the demodulated data.
15 . The receiver according to claim 14 , wherein said shared buffer is further adapted to move a plurality of the chunks to the statically allocated memory.
16 . The receiver according to claim 15 , wherein the plurality of chunks comprises a complete data frame.