IP Library Patent Application 12464917
Patent Application
App. No. 12/464,917

TECHNIQUE FOR REDUCING SILICIDE NON-UNIFORMITIES IN POLYSILICON GATE ELECTRODES BY AN INTERMEDIATE DIFFUSION BLOCKING LAYER

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Patent No.
US None
App. No.
12/464,917
Abstract

Threshold variability in advanced transistor elements, as well as increased leakage currents, may be reduced by incorporating a barrier material in a polysilicon gate electrode. The barrier material results in a well-controllable and well-defined metal silicide in the polysilicon gate electrode during the silicidation sequence and during the further processing by significantly reducing the diffusion of a metal species, such as nickel, into the vicinity of the gate dielectric material.

Claims (28)

1 . A semiconductor device, comprising:

a silicon-containing gate electrode formed above at least a semiconductor region, said silicon-containing gate electrode comprising a first layer comprised of polysilicon and a second layer comprising a metal silicide material, said first and second layers being separated by a barrier material; and

an insulation layer positioned between said silicon-containing gate electrode and said semiconductor region.

2 . The semiconductor device of claim 1 , wherein said metal silicide comprises nickel.

3 . The semiconductor device of claim 1 , wherein said barrier material comprises a metal.

4 . The semiconductor device of claim 3 , wherein said barrier material comprises at least one of tungsten, titanium and cobalt.

5 . The semiconductor device of claim 1 , wherein said barrier material comprises a doped semiconductor material.

6 . The semiconductor device of claim 1 , wherein said gate electrode has a length of approximately 50 nm or less.

7 . The semiconductor device of claim 6 , wherein said length is approximately 30 nm or less.

8 . A method, comprising:

identifying a target depth of a metal silicide region to be formed in a silicon-containing gate electrode;

forming said silicon-containing gate electrode above a semiconductor region so as to include a barrier material at said target depth; and

forming said metal silicide region in said silicon-containing gate electrode above said barrier material.

9 . The method of claim 8 , wherein forming said silicon-containing gate electrode comprises forming a first silicon-containing electrode layer, forming said barrier material on said first silicon-containing electrode layer and forming a second silicon-containing electrode layer.

10 . The method of claim 9 , wherein forming said barrier material on said first silicon-containing layer comprises depositing a conductive material on said first silicon-containing electrode layer having a higher diffusion blocking effect with respect to a metal used for forming said metal silicide region.

11 . The method of claim 10 , wherein said conductive material comprises a metal.

12 . The method of claim 11 , wherein said metal comprises at least one of tungsten and titanium.

13 . The method of claim 9 , wherein forming said barrier material on said first silicon-containing layer comprises incorporating a barrier species through a surface of said first silicon-containing layer.

14 . The method of claim 13 , wherein said barrier species is incorporated by performing a plasma treatment.

15 . The method of claim 8 , wherein forming said silicon-containing gate electrode comprises forming a silicon-containing layer and incorporating a barrier species by performing an ion implantation process so as to form said barrier material.

16 . The method of claim 8 , wherein said metal silicide region is formed by using nickel.

17 . A method, comprising:

forming a layer stack above at least a semiconductor region, said layer stack comprising a first silicon-containing layer, a second silicon-containing layer formed above said first silicon-containing layer and a barrier layer positioned between said first and second silicon-containing layers;

forming a gate electrode from said layer stack; and

forming a metal silicide in said gate electrode.

18 . The method of claim 17 , wherein forming said layer stack comprises depositing said barrier layer on said first silicon-containing layer and depositing said second silicon-containing layer on said barrier layer.

19 . The method of claim 17 , wherein said metal silicide is formed on the basis of nickel.

20 . The method of claim 17 , wherein said barrier layer is provided as a metal-containing material.

Assignments (2)
AFFIRMATION OF PATENT ASSIGNMENT Recorded Aug 18, 2009
From: ADVANCED MICRO DEVICES, INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 023120/0426 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2009
From: GRIEBENOW, UWE; FROHBERG, KAI; RUTTLOFF, KERSTIN
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 022675/0025 →