DMA engine
A circuit and corresponding method for transferring data. The circuit comprises: a CPU; a plurality of addressable devices; and a DMA engine coupled to the CPU and to those devices, the DMA engine comprising a plurality of DMA contexts each having fetch circuitry for fetching a DMA descriptor indicated by the CPU and transfer circuitry for transferring data from one to another of the devices based on a fetched descriptor. The DMA engine further comprises switching means operable to control a group of the contexts to alternate in a complementary sequence between fetching and performing a transfer, such that alternately one or more contexts in the group fetch while one or more others perform a transfer.
1. A circuit comprising:
a CPU;
a plurality of addressable devices; and
a DMA engine coupled to the CPU and to said devices, the DMA engine comprising a plurality of DMA contexts each for fetching a DMA descriptor indicated by the CPU and for transferring data from one to another of said devices based on a fetched descriptor;
wherein the DMA engine further comprises switching means operable to control a group of said contexts to alternate in a complementary sequence between fetching and performing a transfer, such that alternately one or more contexts in the group fetch whilst one or more others perform a transfer.
2. The circuit of claim 1 , wherein the group comprises at least one pair of said contexts, the switching means being operable to control the pair according to said complementary sequence by alternately controlling one context of the pair to fetch a descriptor whilst the other of the pair performs a transfer and vice versa.
3. The circuit of claim 1 , wherein the switching means comprises selection means operable to set the DMA engine into a selected one of: a first mode in which the switching means is configured to control the contexts of said group according to said complementary sequence, and a second mode in which the contexts of said group are allowed to operate independently.
4. The circuit of claim 3 , wherein the selection means comprises a first software-accessible register of at least one bit arranged to set said mode and to be writeable by software executed on the CPU.
5. The circuit of claim 1 , wherein the switching means comprises a second software-accessible register of at least one bit arranged to record which of said group is currently fetching and which of said group is currently performing a transfer, the switching means being arranged to determine which of said group are subsequently to fetch and which are subsequently to perform a transfer in dependence on said second register.
6. The circuit of claim 1 , comprising storage means coupled to the CPU, the switching means comprising software stored in the storage means and arranged such that when executed by the CPU it supplies to the DMA engine a list of descriptors partitioned into a separate linked list for each context of said group so as to control the contexts to operate in said complementary sequence.
7. The circuit of claim 1 , wherein said CPU, devices and DMA engine are integrated onto the same integrated circuit.
8. The circuit of claim 1 , wherein one of said devices comprises an RF interface, and the CPU is programmed to execute code to operate the DMA engine to transfer data between the RF interface and another of said devices, using said complementary sequence, in order to communicate over a wireless cellular network.
9. A method of transferring data, the method comprising:
supplying an indication of a plurality of DMA descriptors to a DMA engine comprising a plurality of DMA contexts; and
operating a group of said contexts to each fetch a respective one or more of the indicated descriptors and based thereon to perform a corresponding one or more transfers of data from one to another of a plurality of addressable devices;
wherein said operation of the group comprises controlling the contexts of the group to alternate in a complementary sequence between fetching and performing a transfer, such that alternately one or more contexts in the group fetch whilst one or more others perform a transfer.
10. The method of claim 9 , wherein the group comprises at least one pair of said contexts, and said operation of the group comprises controlling the pair according to said complementary sequence by alternately controlling one context of the pair to fetch a descriptor whilst the other of the pair performs a transfer and vice versa.
11. The method of claim 9 , comprising changing between: a first mode in which said operation of the group comprises controlling the contexts of said group according to said complementary sequence, and a second mode in which the contexts of said group are allowed to operate independently.
12. The method of claim 11 , wherein the changing between the modes comprises executing software to write to a first register of at least one bit arranged to set said mode.
13. The method of claim 9 , comprising executing software to write to a second register of at least one bit to record which of said group is currently fetching and which of said group is currently performing a transfer, wherein said operation of the group comprises determining which of said group are subsequently to fetch and which are subsequently to perform a transfer in dependence on said second register.
14. The method of claim 9 , wherein said operation of the group comprise supplying to the DMA engine a list of descriptors partitioned into a separate linked list for each context of said group so as to control the contexts to operate in said complementary sequence.
15. The method of claim 9 , performed on a DMA engine integrated onto the same integrated circuit as an associated CPU and said devices.
16. The method of claim 9 , wherein one of said devices comprises an RF interface, and method comprises executing software to operate the DMA engine to transfer data between the RF interface and another of said devices, using said complementary sequence, in order to communicate over a wireless cellular network.
17. A user equipment comprising:
a CPU;
a plurality of addressable devices; and
a DMA engine coupled to the CPU and to said devices, the DMA engine comprising a plurality of DMA contexts each for fetching a DMA descriptor indicated by the CPU and for transferring data from one to another of said devices based on a fetched descriptor;
wherein the DMA engine further comprises switching means operable to control a group of said contexts to alternate in a complementary sequence between fetching and performing a transfer, such that alternately one or more contexts in the group fetch whilst one or more others perform a transfer.
18. A computer program product for transferring data, the program comprising code which when executed by a processor performs the steps of:
supplying an indication of a plurality of DMA descriptors to a DMA engine comprising a plurality of DMA contexts; and
operating a group of said contexts to each fetch a respective one or more of the indicated descriptors and based thereon to perform a corresponding one or more transfers of data from one to another of a plurality of addressable devices;
wherein said operation of the group comprises operating a switching means to control the contexts of the group to alternate in a complementary sequence between fetching and performing a transfer, such that alternately one or more contexts in the group fetch whilst one or more others perform a transfer.