IP Library Granted Patent US 9,299,661
Granted Patent B2
US 9,299,661 · App. 12/467,748 · Granted Mar 29, 2016

Integrated circuit package and method of making same

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,299,661
App. No.
12/467,748
Granted
Mar 29, 2016
Kind
B2
Abstract

An integrated circuit package includes a first dielectric layer comprising a dielectric film having a first side and a second side. The package also includes a die having an active surface affixed to a contact location of the first side of the dielectric film. A die stud is affixed to the active surface of the die and extends through the dielectric film to an interconnect location of the second side of the dielectric film.

Claims (53)

1. An apparatus comprising:

a first dielectric layer comprising a dielectric film having a first side and a second side;

a die having an active surface affixed to a contact location of the first side of the dielectric film such that the active surface of the die is in direct contact with the first side of the dielectric film;

a die stud affixed to the active surface of the die and extending through the dielectric film to an interconnect location of the second side of the dielectric film; and

an embedding compound encapsulating the die and coating a portion of the first side of the dielectric film outside the contact location; and

wherein a bottom-most surface of the die stud is affixed to the active surface of the die and a top-most surface of the die stud is substantially coplanar with the second side of the dielectric film.

2. The apparatus of claim 1 further comprising a die pad affixed to the active surface of the die, and wherein the die stud is affixed to the die pad.

3. The apparatus of claim 1 further comprising a metal cladding affixed to the second side of the dielectric film such that a first surface the metal cladding is in direct physical contact with the second side of the dielectric film.

4. The apparatus of claim 3 further comprising a second dielectric layer comprising a dielectric material affixed to the metal-cladding such that the second dielectric layer is in direct physical contact with a second surface of the metal cladding.

5. The apparatus of claim 3 wherein a portion of the metal-cladding extends into the interconnect location of the second side of the dielectric film.

6. The apparatus of claim 5 wherein the metal-cladding is electrically coupled to the die stud.

7. The apparatus of claim 3 wherein the metal-cladding comprises an alignment pad positioned at a pre-determined alignment location of the second side of the dielectric film.

8. The apparatus of claim 1 wherein the die stud comprises a metal stud bump.

9. The apparatus of claim 1 wherein the die stud comprises a proud sputter-plated metal pad; and

wherein the metal pad is in direct physical contact with the dielectric film.

10. The apparatus of claim 1 wherein the dielectric film comprises one of a thermoset material and a thermoplastic material.

11. A method of fabricating an integrated circuit (IC) package comprising:

providing an electrical component having an attachment stud affixed thereto; and

affixing the electrical component to a first surface of a dielectric film via an adhesive property of the dielectric film such that the attachment stud of the electrical component extends through the dielectric film.

12. The method of claim 11 further comprising:

pressing the electrical component into the dielectric film; and

removing an excess portion of the attachment stud.

13. The method of claim 11 further comprising selectively removing a portion of a metal-clad layer affixed to the second surface of the dielectric layer.

14. The method of claim 13 wherein removing a portion of the metal-clad layer comprises forming an electrical interconnect path coupled to the attachment stud.

15. The method of claim 13 wherein removing a portion of the metal-clad layer comprises forming an alignment pad at a pre-determined alignment location.

16. The method of claim 15 further comprising affixing a removable support layer to the metal-clad layer.

17. The method of claim 15 further comprising forming a metallization layer on the second surface of the dielectric layer.

18. The method of claim 11 further comprising encapsulating a non-active surface of the electrical component and a portion of the first surface of the dielectric layer in an embedding compound.

19. The method of claim 11 further comprising curing the dielectric film after pressing the electrical component thereinto.

20. The method of claim 11 further comprising removing a portion of bulk material from the electrical component to reduce an overall height of the IC package.

21. An apparatus comprising:

a dielectric film having substantially uniform material properties throughout a thickness of the dielectric film, wherein the thickness is defined between a first side and a second side of the dielectric film;

a plurality of components affixed to the first side of the dielectric film via an adhesive property of the dielectric film and absent a layer of adhesive between the plurality of components and the dielectric film that is distinct from a property of the dielectric film;

at least one attachment stud affixed to a top surface of a contact pad of each of the plurality of components;

a metal-clad layer having a bottom surface directly affixed to the second side of the dielectric film; and

wherein the entire volume of the at least one attachment stud is positioned between a lower plane defined by the top surface of the contact pad and an upper plane defined by the bottom surface of the metal-clad layer; and

wherein the dielectric film and the plurality of components are embedded within a multi-layer printed circuit.

22. The apparatus of claim 21 wherein the metal-clad layer is electrically coupled to the at least one attachment stud; and

wherein the at least one attachment stud comprises a metal stud bump.

23. The apparatus of claim 21 wherein the dielectric film comprises one of a thermoset material and a thermoplastic material.

24. The apparatus of claim 1 wherein the dielectric film is absent a layer of adhesive that is distinct from the material of the dielectric film.

25. The apparatus of claim 1 wherein a via is formed through the dielectric film by the die stud.

26. The method of claim 19 wherein curing further comprises curing the embedding compound.

27. The apparatus of claim 21 wherein a via is formed through the dielectric film by the at least one attachment stud.

28. A method of fabricating an integrated circuit (IC) package comprising:

affixing an attachment stud to a contact pad of a die;

removing a release liner from a first side of a dielectric film, the dielectric film having a metal cladding on a second side thereof; and

coupling the attachment stud with the dielectric film such that the attachment stud is in direct physical contact with the metal cladding and forms an electrical contact with the metal cladding.

29. The method of claim 28 wherein removing the release liner from the first side of the dielectric film comprises removing the release liner from the first side of one of a b-stage epoxy and a thermoplastic material; and

wherein coupling the attachment stud with the dielectric film comprises pressing the attachment stud through the dielectric film from the first side.

30. The method of claim 28 wherein affixing the attachment stud comprises wirebonding a gold stud bump.

31. The method of claim 28 wherein affixing the attachment stud comprises sputter-plating a proud plated pad.

32. The method of claim 11 wherein affixing comprises affixing the electrical component to the first surface of the dielectric film such that an active surface of the electrical component is in direct contact with the first surface of the dielectric film.

Assignments (3)
CHANGE OF NAME Recorded Jun 23, 2025
From: GE INTELLECTUAL PROPERTY LICENSING, LLC
To: DOLBY INTELLECTUAL PROPERTY LICENSING, LLC
Reel/Frame 071692/0511 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2025
From: GENERAL ELECTRIC COMPANY
To: GE INTELLECTUAL PROPERTY LICENSING, LLC
Reel/Frame 071704/0816 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2025
From: DOLBY INTELLECTUAL PROPERTY LICENSING, LLC
To: EDISON INNOVATIONS, LLC
Reel/Frame 071674/0420 →